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...=============================== --- lib/Bitcode/Reader/BitcodeReader.cpp (revision 98552) +++ lib/Bitcode/Reader/BitcodeReader.cpp (working copy) @@ -293,6 +293,8 @@ } else if (ConstantStruct *UserCS = dyn_cast<ConstantStruct>(UserC)) { NewC = ConstantStruct::get(Context, &NewOps[0], NewOps.size(), UserCS->getType()->isPacked()); + } else if (ConstantUnion *UserCU = dyn_cast<ConstantUnion>(UserC)) { + NewC = ConstantUnion::get(UserCU->getType(), NewOps[0]); } else if (isa<ConstantVector>(User...

...addrec are guaranteed to have no overflow. // // No self-wrap cannot be guaranteed after changing the step size, but // will be inferred if either NUW or NSW is true. Flags = AddRec->getNoWrapFlags(clearFlags(Flags, SCEV::FlagNW)); const SCEV *NewRec = getAddRecExpr(NewOps, AddRecLoop, Flags); // If all of the other operands were loop invariant, we are done. if (Ops.size() == 1) return NewRec; I understand that you can't assume it won't wrap around with the new stride, but I couldn't find anything else later that would re-assign NSW/NUW. Ma...

Hello, I noticed a bit of a gap in the current code for unions: a ConstantUnion cannot be written out to .ll. Hopefully I'm not stepping on Talin's toes by posting this, it's a fairly straightforward adaptation of the code for structs just above. Tim. -- The University of Edinburgh is a charitable body, registered in Scotland, with registration number SC005336. --------------

...have no overflow. > // > // No self-wrap cannot be guaranteed after changing the step size, but > // will be inferred if either NUW or NSW is true. > Flags = AddRec->getNoWrapFlags(clearFlags(Flags, SCEV::FlagNW)); > const SCEV *NewRec = getAddRecExpr(NewOps, AddRecLoop, Flags); > > // If all of the other operands were loop invariant, we are done. > if (Ops.size() == 1) return NewRec; > > I understand that you can't assume it won't wrap around with the new stride, but I couldn't find anything else later that wo...

...tedBitwiseLogic()` there happens a reverse of the above unfolding, which transforms `logic(cast(A), cast(B))` to `cast(logic(A, B))`: ``` if ((!isa<ICmpInst>(Cast0Src) || !isa<ICmpInst>(Cast1Src)) && shouldOptimizeCast(Cast0) && shouldOptimizeCast(Cast1)) { Value *NewOp = Builder->CreateBinOp(LogicOpc, Cast0Src, Cast1Src, I.getName()); return CastInst::Create(CastOpcode, NewOp, DestTy); } ``` The `(!isa<ICmpInst>(Cast0Src) || !isa<ICmpInst>(Cast1Src))` part has been added by r48715 in order to ensure that Ins...

On 16 November 2013 06:56, Andrew Trick <atrick at apple.com> wrote: > - getMulExpr constructs a new AddRec with NSW: > > Flags = AddRec->getNoWrapFlags(clearFlags(Flags, SCEV::FlagNW)); > const SCEV *NewRec = getAddRecExpr(NewOps, AddRecLoop, Flags); > Hi Andrew, Thanks for looking at this. Clearing the flags here makes sense, but it's being too conservative. I'm thinking I'll need something like propagateSafeFlags(...) with knowledge of the loop induction ranges or something else instead of simply relyin...

Hi Daniel, I defined checkEarlyTargetMatchPredicate() to explicitly check for the tied operands, and it worked. I could define an alias like: InstAlias<"oldOP $rd, $rd, $rs1", (NEWOP $rd, $rs1)> However, I had to additionally change AsmMatcherEmitter 'Hack' variable setting to allow the repeated operand $rd in the AsmString. Do you or anyone else know the history with this 'Hack' flag? Thanks, Ana. diff --git a/utils/TableGen/AsmMatcherEmitter.cpp b/ut...

...happens a reverse of the above unfolding, which transforms `logic(cast(A), cast(B))` to `cast(logic(A, B))`: > > ``` > if ((!isa<ICmpInst>(Cast0Src) || !isa<ICmpInst>(Cast1Src)) && > shouldOptimizeCast(Cast0) && shouldOptimizeCast(Cast1)) { > Value *NewOp = Builder->CreateBinOp(LogicOpc, Cast0Src, Cast1Src, > I.getName()); > return CastInst::Create(CastOpcode, NewOp, DestTy); > } > ``` > > The `(!isa<ICmpInst>(Cast0Src) || !isa<ICmpInst>(Cast1Src))` part has been added by r487...

...gt; wrote: > >> On 16 November 2013 06:56, Andrew Trick <atrick at apple.com> wrote: >> - getMulExpr constructs a new AddRec with NSW: >> >> Flags = AddRec->getNoWrapFlags(clearFlags(Flags, SCEV::FlagNW)); >> const SCEV *NewRec = getAddRecExpr(NewOps, AddRecLoop, Flags); > > Hi Andrew, > > Thanks for looking at this. > > Clearing the flags here makes sense, but it's being too conservative. I'm thinking I'll need something like propagateSafeFlags(...) with knowledge of the loop induction ranges or something else...

...ot;); > // FIXME: Should reject these. The ARM backend hits this with $lane in a > // bunch of instructions. It is unclear what the right answer is. > … > > Is there a way to fix this limitation? > > I would like to express: InstAlias<(opcode $rd, $rd, $rs1), (newopcode $rd, $rs1)> > > Thank you, > Ana. > > > -- > Ana Pazos > Qualcomm Innovation Center, Inc. > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, > a Linux Foundation Collaborative Project. > _______________________________________________ &g...

...39; can never be matched!"); // FIXME: Should reject these. The ARM backend hits this with $lane in a // bunch of instructions. It is unclear what the right answer is. … Is there a way to fix this limitation? I would like to express: InstAlias<(opcode $rd, $rd, $rs1), (newopcode $rd, $rs1)> Thank you, Ana. -- Ana Pazos Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.

The LangRef says this for left shifts: "If the nsw keyword is present, then the shift produces a poison value if it shifts out any bits that disagree with the resultant sign bit." ... (1) followed by "As such, NUW/NSW have the same semantics as they would if the shift were expressed as a mul instruction with the same nsw/nuw bits in (mul %op1, (shl 1, %op2))." ... (2) But

...above unfolding, which transforms `logic(cast(A), cast(B))` to `cast(logic(A, B))`: > > > > ``` > > if ((!isa<ICmpInst>(Cast0Src) || !isa<ICmpInst>(Cast1Src)) && > > shouldOptimizeCast(Cast0) && shouldOptimizeCast(Cast1)) { > > Value *NewOp = Builder->CreateBinOp(LogicOpc, Cast0Src, Cast1Src, > > I.getName()); > > return CastInst::Create(CastOpcode, NewOp, DestTy); > > } > > ``` > > > > The `(!isa<ICmpInst>(Cast0Src) || !isa<ICmpInst>(Cast1Src))...

Hi, I’m looking at RegBankSelect’s partially implemented support for deciding to split a value between multiple registers and I’m wondering if it’s actually intended to solve the problem I’m trying to use it for. RegisterBankInfo.h has this example mapping table: /// E.g., /// Let say we have a 32-bit add and a <2 x 32-bit> vadd. We /// can expand the /// <2 x 32-bit> add into

LLVM is built in Release mode. The version is 6.0.0. I think that a similar code worked on verison 3.9.0. It is probably a null pointer dereference occurring in eraseFromParent(). I checked and reconfirmed that the instruction had no uses. Perhaps I should rebuild LLVM. Thanks. On Wed, Aug 8, 2018 at 9:03 PM, mayuyu.io <admin at mayuyu.io> wrote: > Hmmmm that’s strange. Do you get an

On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote: > Can you explain why you chose the approach of using a new pass? > I pictured removing LegalizeDAG's type legalization code would > mostly consist of finding all the places that use TLI.getTypeAction > and just deleting code for handling its Expand and Promote. Are you > anticipating something more

On May 20, 2009, at 1:34 PM, Eli Friedman wrote: > On Wed, May 20, 2009 at 1:19 PM, Eli Friedman > <eli.friedman at gmail.com> wrote: > >> Per subject, this patch adding an additional pass to handle vector >> >> operations; the idea is that this allows removing the code from >> >> LegalizeDAG that handles illegal types, which should be a significant

...pes doesn't make any sense to me - assert(0 && "Unexpected operation in WidenVectorOp!"); - break; - case ISD::UNDEF: - Result = DAG.getUNDEF(WidenVT); - break; - case ISD::BUILD_VECTOR: { - // Build a vector with undefined for the new nodes - SDValueVector NewOps(Node->op_begin(), Node->op_end()); - for (unsigned i = NumElts; i < NewNumElts; ++i) { - NewOps.push_back(DAG.getUNDEF(EVT)); - } - Result = DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, - &NewOps[0], NewOps.size()); - break; - } - case ISD::IN...