Displaying 8 results from an estimated 8 matches for "new_immediatevalu".
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new_immediatevalue
2014 Jun 03
8
[PATCH v2 0/4] Constant folding of new Instructions
And another try for constant folding of Instructions for nvc0.
Please Review this!
Thanks,
Tobias Klausmann
Tobias Klausmann (4):
nvc0/ir: clear subop when folding constant expressions
nvc0/ir: Handle reverse subop for OP_EXTBF when folding constant
expressions
nvc0/ir: Handle OP_BFIND when folding constant expressions
nvc0/ir: Handle OP_POPCNT when folding constant expressions
2015 Mar 25
0
[PATCH] nv50/ir: take postFactor into account when doing peephole optimizations
...= a->data.f64 * b->data.f64; break;
case TYPE_S32:
if (i->subOp == NV50_IR_SUBOP_MUL_HIGH) {
@@ -579,6 +581,7 @@ ConstantFolding::expr(Instruction *i,
i->src(0).mod = Modifier(0);
i->src(1).mod = Modifier(0);
+ i->postFactor = 0;
i->setSrc(0, new_ImmediateValue(i->bb->getProgram(), res.data.u32));
i->setSrc(1, NULL);
@@ -682,7 +685,7 @@ ConstantFolding::tryCollapseChainedMULs(Instruction *mul2,
Instruction *insn;
Instruction *mul1 = NULL; // mul1 before mul2
int e = 0;
- float f = imm2.reg.data.f32;
+ float f = imm2.reg.data....
2014 May 18
1
[PATCH 1/2] nv50/ir: fix s32 x s32 -> high s32 multiply logic
Retrieving the high 32 bits of a signed multiply is rather annoying. It
appears that the simplest way to do this is to compute the absolute
value of the arguments, and perform a u32 x u32 -> u64 operation. If the
arguments' signs differ, then negate the result. Since there is no u64
support in the cvt instruction, we have the perform the 2's complement
negation "by hand".
2014 Jun 03
0
[PATCH v2 4/4] nvc0/ir: Handle OP_POPCNT when folding constant expressions
...urn;
}
@@ -966,6 +970,17 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
i->subOp = 0;
break;
}
+ case OP_POPCNT: {
+ uint32_t res;
+ if (!i->srcExists(1)) {
+ res = util_bitcount(imm0.reg.data.u32);
+ i->setSrc(0, new_ImmediateValue(i->bb->getProgram(), res));
+ i->setSrc(1, NULL);
+ i->op = OP_MOV;
+ i->subOp = 0;
+ }
+ break;
+ }
default:
return;
}
--
1.8.4.5
2014 Jun 03
0
[PATCH v2 3/4] nvc0/ir: Handle OP_BFIND when folding constant expressions
...ast_bit_signed(imm0.reg.data.s32) - 1; break;
+ case TYPE_U32:
+ res = util_last_bit(imm0.reg.data.u32) -1; break;
+ default:
+ return;
+ }
+ if ((i->subOp == NV50_IR_SUBOP_BFIND_SAMT) && (res >= 0))
+ res = 31 - res;
+ i->setSrc(0, new_ImmediateValue(i->bb->getProgram(), (uint32_t)res));
+ i->setSrc(1, NULL);
+ i->op = OP_MOV;
+ i->subOp = 0;
+ break;
+ }
default:
return;
}
--
1.8.4.5
2015 Aug 19
5
[PATCH 1/2] nvc0/ir: detect AND/SHR pairs and convert into EXTBF
...0.reg.data.f32 != 1.0)
- return;
- if (i->getSrc(t)->getInsn()->dType != TYPE_U32)
- return;
+ Instruction *src = i->getSrc(t)->getInsn();
+ ImmediateValue imm1;
+ if (imm0.reg.data.u32 == 0) {
+ i->op = OP_MOV;
+ i->setSrc(0, new_ImmediateValue(prog, 0u));
+ i->src(0).mod = Modifier(0);
+ i->setSrc(1, NULL);
+ } else if (imm0.reg.data.u32 == ~0U) {
+ i->op = i->src(t).mod.getOp();
+ if (t) {
+ i->setSrc(0, i->getSrc(t));
+ i->src(0).mod = i->src(t).mod;
+...
2017 Mar 26
5
[PATCH v5 0/5] nvc0/ir: add support for MAD/FMA PostRALoadPropagation
was "nv50/ir: PostRaConstantFolding improvements" before.
nothing really changed from the last version, just minor things.
Karol Herbst (5):
nv50/ir: restructure and rename postraconstantfolding pass
nv50/ir: implement mad post ra folding for nvc0+
gk110/ir: add LIMM form of mad
gm107/ir: add LIMM form of mad
nv50/ir: also do PostRaLoadPropagation for FMA
2014 Jun 03
6
[PATCH v3 0/4] Constant folding of new Instructions
Yet another try for constant folding of Instructions for nvc0.
Please Review this again! (Hopefully the last time ;-) )
Tobias Klausmann (4):
nvc0/ir: clear subop when folding constant expressions
nvc0/ir: Handle reverse subop for OP_EXTBF when folding constant
expressions
nvc0/ir: Handle OP_BFIND when folding constant expressions
nvc0/ir: Handle OP_POPCNT when folding constant