Displaying 8 results from an estimated 8 matches for "nerrb".
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herrb
2010 Sep 29
2
[LLVMdev] comparison pattern trouble
Our architecture has 1-bit boolean predicate registers.
I've defined comparison
def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>;
But then I end up having the following bug:
Code
%0 = zext i8 %data to i32
%1 = zext i16 %crc to i32
%2 = xor i32 %1, %0
%3 = and i32 %2, 1...
2010 Sep 29
1
[LLVMdev] comparison pattern trouble - might be a bug in LLVM 2.8?
On 29 Sep 2010, at 06:25, Heikki Kultala wrote:
> Our architecture has 1-bit boolean predicate registers.
>
> I've defined comparison
>
>
> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>;
>
>
>
>
> But then I end up having the following bug:
>
>
> Code
>
>
> %0 = zext i8 %data to i32
> %1 = zext i16...
2010 Oct 01
2
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG? (Re: comparison pattern trouble - might be a bug in LLVM 2.8?)
...wrote:
>>>
>>>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote:
>>>>
>>>>> Our architecture has 1-bit boolean predicate registers.
>>>>>
>>>>> I've defined comparison
>>>>>
>>>>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>;
>>>>>
>>>>> But then I end up having the following bug:
>>>>>
>>>>> Code
>>>>>
&...
2010 Oct 04
2
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG
...tala wrote:
>>>
>>>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote:
>>>>
>>>>> Our architecture has 1-bit boolean predicate registers.
>>>>>
>>>>> I've defined comparison
>>>>>
>>>>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>;
>>>>>
>>>>> But then I end up having the following bug:
>>>>>
>>>>> Code
>>>>>
>...
2010 Sep 29
0
[LLVMdev] comparison pattern trouble - might be a bug in LLVM 2.8?
On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote:
> On 29 Sep 2010, at 06:25, Heikki Kultala wrote:
>
>> Our architecture has 1-bit boolean predicate registers.
>>
>> I've defined comparison
>>
>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>;
>>
>> But then I end up having the following bug:
>>
>> Code
>>
>> %0 = zext i8 %data to i32
>> %1 = zext i16 %cr...
2010 Sep 30
4
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG? (Re: comparison pattern trouble - might be a bug in LLVM 2.8?)
...l Wendling wrote:
> On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote:
>
>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote:
>>
>>> Our architecture has 1-bit boolean predicate registers.
>>>
>>> I've defined comparison
>>>
>>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>;
>>>
>>> But then I end up having the following bug:
>>>
>>> Code
>>>
>>> %0 = zext i8 %data to i32
>&...
2010 Oct 01
0
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG? (Re: comparison pattern trouble - might be a bug in LLVM 2.8?)
...010, at 12:36 AM, Heikki Kultala wrote:
>>
>>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote:
>>>
>>>> Our architecture has 1-bit boolean predicate registers.
>>>>
>>>> I've defined comparison
>>>>
>>>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>;
>>>>
>>>> But then I end up having the following bug:
>>>>
>>>> Code
>>>>
>>>> %0 =...
2010 Oct 04
0
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG
...t;>>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote:
>>>>>
>>>>>> Our architecture has 1-bit boolean predicate registers.
>>>>>>
>>>>>> I've defined comparison
>>>>>>
>>>>>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>;
>>>>>>
>>>>>> But then I end up having the following bug:
>>>>>>
>>>>>> Code
>>...