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Bugs 1519 and 1521 currently prevent a clean bootstrap on Linux x86_64. I was able to hack it to work :-) The attached patch includes two parts. One is a tentative fix bug 1519: just set LastFieldStartsAtNonByteBoundry in allFieldsAreNotBitFields. The other one is a plain hack. llvm-gcc and gcc disagree on how to pass some structures, so stage2 gcc fails to use the libcpp compiled by gcc. So I

On Fri, 21 Apr 2006, [UTF-8] Rafael Esp?ndola wrote: > To work aroud the problem I edited gcc/objc/config-lang.in and removed > the comment from the line > #target_libs=target-libobjc > > With this change it is again possible to build without objc. The > complete configure line was > > ../llvm-gcc4-1.7.source/configure...

...So I just edited llvm-gcc4-1.7.source/gcc/Makefile.in and a line like this: INCLUDES += -I$(LLVMOBJDIR)/include With this change, the building errors were gone. Is this the right hack? Thanks. Nai On Friday 28 April 2006 08:05, Chris Lattner wrote: > On Fri, 21 Apr 2006, [UTF-8] Rafael Esp?ndola wrote: > > To work aroud the problem I edited gcc/objc/config-lang.in and removed > > the comment from the line > > #target_libs=target-libobjc > > > > With this change it is again possible to build without objc. The > > complete configure line was > > >...

On Wed, 6 Sep 2006, [UTF-8] Rafael Esp?ndola wrote: > The ARM has some very powerful and complex addressing modes. For > example, the data processing instructions (and, orr, add, ..) have an > addressing mode that has 11 options (imm, reg, and 9 reg + some > shift). > > I am considering 3 ways to implement this: > > 1...

On Fri, 8 Sep 2006, [UTF-8] Rafael Esp?ndola wrote: > I am not sure if it is the correct solution, but the attached patch > fixes the problem. Your solution is correct, in that it will work and follows with the current ifdef approach. I applied this patch though, which doesn't use the ifdefs, hopefully it is more robust: http://...

On Wed, 6 Dec 2006, [UTF-8] Rafael Esp?ndola wrote: > In the ARM backend, functions (and other 32 bit constants) are placed > in a pool and loaded when needed. Has this approach been replaced with your later constant pool patch? -Chris > A problem with this is that ".weak" directives must be printed in the > pool. Thi...

On Thu, 21 Jun 2007, [UTF-8] Rafael Esp?ndola wrote: > Bugs 1519 and 1521 currently prevent a clean bootstrap on Linux > x86_64. I was able to hack it to work :-) > > The attached patch includes two parts. One is a tentative fix bug > 1519: just set LastFieldStartsAtNonByteBoundry in > allFieldsAreNotBitFields. Cool, I'l...

In the ARM backend, functions (and other 32 bit constants) are placed in a pool and loaded when needed. A problem with this is that ".weak" directives must be printed in the pool. This is not supported in the standard printer, so I think that I have found the first use for MachineConstantPoolValue :-) Creating the constant is easy, but I have two problems: 1) what are the methods

On Sun, 17 Sep 2006, [UTF-8] Rafael Esp?ndola wrote: > The ARM has a multiply instruction of the form Rd=Rm*Rs where Rd != Rm. > How can I add this requirement to the instruction definition? Unfortunately there is currently no great way to do this. Some options are: 1. Pin one operand to a specific register, one that isn't alloc...

Building with --enable-llvm failed latter on when compiling libojc: configure:5099: checking for exception model to use configure:5131: /home/rafael/dev/gcc/build/gcc/xgcc -B/home/rafael/dev/gcc/build/gcc/ -B/i686-pc-linux-gnu/bin/ -B/i686-pc-linux-gnu/lib/ -isystem /i686-pc-linux-gnu/include -isystem /i686-pc-linux-gnu/sys-include -c -xobjecti ve-c -fgnu-runtime -fobjc-exceptions -S conftest.c

The ARM has a multiply instruction of the form Rd=Rm*Rs where Rd != Rm. How can I add this requirement to the instruction definition? Thanks, Rafael

> Funny, I've just got one student for exactly same task -- writing ARM > backend. Of course, the student might well disappear by the time new term > begins and might not produce anything usable for a year ;-) I am currently reading and hacking the code. I would be very glad to work with your student if that is not a problem. > I wrote one backend (private) in a couple of months.

On Wed, 31 May 2006, [UTF-8] Rafael Esp?ndola wrote: >> We don't want the copy and shift to wander apart from each other (e.g. we >> don't want another shift to get scheduled in between them), so we flag >> them together. In practice, these copies usually get coallesced away. > In the second case shl explicitly us...

The ARM has some very powerful and complex addressing modes. For example, the data processing instructions (and, orr, add, ..) have an addressing mode that has 11 options (imm, reg, and 9 reg + some shift). I am considering 3 ways to implement this: 1) define one instruction that has an ARM specific addressing mode that covers all 11 possibilities. 2) define 11 instructions. 3) a mix of the two

On 5/31/06, Chris Lattner <sabre at nondot.org> wrote: > On Wed, 31 May 2006, [UTF-8] Rafael Esp?ndola wrote: > >> We don't want the copy and shift to wander apart from each other (e.g. we > >> don't want another shift to get scheduled in between them), so we flag > >> them together. In practice, these copies usually get coallesced away. > > In the second ca...

> > Why it is named RETFLAG? > > Historical reason. Originally we didn't have nodes that could > *optionally* have an input flag. A better design, e.g. on PPC would be to > have a PPCISD::RET node, which takes an optional input flag, and always > lower RET to it. I See. I will try to always lower to "(mov)*;bx lr" on ARM. > Flag in the SelectionDAG stuff is

Hi Chris, > On Sun, 17 Sep 2006, [UTF-8] Rafael Esp?ndola wrote: > > The ARM has a multiply instruction of the form Rd=Rm*Rs where Rd != > > Rm. How can I add this requirement to the instruction definition? > > ... > > I'd like to make the regalloc interfaces more powerful to be able to > capture this sort of thing, but I...

I am trying to build llvm-gcc4 on a amd64. I had to add the attached patch to get the build system to select the correct library. Now the build fails while compiling a code that has __builtin_va_copy. The attached test.i fails with: cc1: ../../trunk/gcc/llvm-convert.cpp:443: llvm::Value* TreeToLLVM::Emit(tree_node*, llvm::Value*): Assertion `(isAggregateType(((exp)->common.type)) == (DestLoc

...specific > than "Re: Contents of LLVMdev digest..." > > > Today's Topics: > > 1. Re: Dead node removal in DAGCombiner (Akira Hatanaka) > 2. Re: Is LLVM compatible with AMD? (Villmow, Micah) > 3. Re: Segmented Stacks (Re-Roll 2) (Rafael ?vila de Esp?ndola) > 4. How much adaptable is the LLVM to POSIX pattern? > (geovanisouza92 at gmail.com) > 5. Re: Why BinaryOperator::Create requires same argument types > for shifts? (Yuri) > 6. Re: Why BinaryOperator::Create requires same argument types > for shifts? (E...

On 19/12/11 08:17 PM, Carter, Jack wrote: > Proposal for ELF text and data big endian support for direct object generation Looks like the basic support is already there. If I remember correctly, what we have lets us produce a hello world on a big endian freebsd powerpc. > Cheers, > > Jack Cheers, Rafael