Displaying 20 results from an estimated 53 matches for "native_write_cr3".
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native_write_cr2
2012 Nov 16
1
[PATCH v4] x86/xen: Use __pa_symbol instead of __pa on C visible symbols
...a(level3_user_vsyscall) | _PAGE_TABLE);
+ __pgd(__pa_symbol(level3_user_vsyscall) |
+ _PAGE_TABLE);
ret = 0;
}
@@ -1958,10 +1959,10 @@ void __init xen_setup_kernel_pagetable(pgd_t *pgd, unsigned long max_pfn)
* pgd.
*/
if (xen_feature(XENFEAT_writable_page_tables)) {
- native_write_cr3(__pa(init_level4_pgt));
+ native_write_cr3(__pa_symbol(init_level4_pgt));
} else {
xen_mc_batch();
- __xen_write_cr3(true, __pa(init_level4_pgt));
+ __xen_write_cr3(true, __pa_symbol(init_level4_pgt));
xen_mc_issue(PARAVIRT_LAZY_CPU);
}
/* We can't that easily rip out L3 and L2,...
2012 Nov 16
1
[PATCH v4] x86/xen: Use __pa_symbol instead of __pa on C visible symbols
...a(level3_user_vsyscall) | _PAGE_TABLE);
+ __pgd(__pa_symbol(level3_user_vsyscall) |
+ _PAGE_TABLE);
ret = 0;
}
@@ -1958,10 +1959,10 @@ void __init xen_setup_kernel_pagetable(pgd_t *pgd, unsigned long max_pfn)
* pgd.
*/
if (xen_feature(XENFEAT_writable_page_tables)) {
- native_write_cr3(__pa(init_level4_pgt));
+ native_write_cr3(__pa_symbol(init_level4_pgt));
} else {
xen_mc_batch();
- __xen_write_cr3(true, __pa(init_level4_pgt));
+ __xen_write_cr3(true, __pa_symbol(init_level4_pgt));
xen_mc_issue(PARAVIRT_LAZY_CPU);
}
/* We can't that easily rip out L3 and L2,...
2017 Oct 25
0
[PATCH 03/13] x86/paravirt: Convert native patch assembly code strings to macros
...RESTORE_FL "push " _REG_ARG1 "; popf"
> +#define NATIVE_IRQ_DISABLE "cli"
> +#define NATIVE_IRQ_ENABLE "sti"
> +#define NATIVE_READ_CR2 "mov %cr2, " _REG_RET
> +#define NATIVE_READ_CR3 "mov %cr3, " _REG_RET
> +#define NATIVE_WRITE_CR3 "mov " _REG_ARG1 ", %cr3"
> +#define NATIVE_FLUSH_TLB_SINGLE "invlpg (" _REG_ARG1 ")"
> +#define NATIVE_SWAPGS "swapgs"
> +#define NATIVE_IRET "iret"
> +#define NATIVE_QUEUED_SPIN_UNLOCK "movb $0, (" _REG_ARG1 &...
2017 Oct 04
1
[PATCH 03/13] x86/paravirt: Convert native patch assembly code strings to macros
..._REG_RET
+#define NATIVE_RESTORE_FL "push " _REG_ARG1 "; popf"
+#define NATIVE_IRQ_DISABLE "cli"
+#define NATIVE_IRQ_ENABLE "sti"
+#define NATIVE_READ_CR2 "mov %cr2, " _REG_RET
+#define NATIVE_READ_CR3 "mov %cr3, " _REG_RET
+#define NATIVE_WRITE_CR3 "mov " _REG_ARG1 ", %cr3"
+#define NATIVE_FLUSH_TLB_SINGLE "invlpg (" _REG_ARG1 ")"
+#define NATIVE_SWAPGS "swapgs"
+#define NATIVE_IRET "iret"
+#define NATIVE_QUEUED_SPIN_UNLOCK "movb $0, (" _REG_ARG1 ")"
+
/*...
2007 Apr 18
1
[PATCH] paravirt build fix
...d native_write_cr0(unsigned long val);
-fastcall unsigned int native_read_cr2(void);
-fastcall void native_write_cr2(unsigned int val);
+fastcall unsigned long native_read_cr2(void);
+fastcall void native_write_cr2(unsigned long val);
-fastcall unsigned int native_read_cr3(void);
-fastcall void native_write_cr3(unsigned int val);
+fastcall unsigned long native_read_cr3(void);
+fastcall void native_write_cr3(unsigned long val);
-fastcall unsigned int native_read_cr4(void);
-fastcall unsigned int native_read_cr4_safe(void);
-fastcall void native_write_cr4(unsigned int val);
+fastcall unsigned long native_...
2007 Apr 18
1
[PATCH] paravirt build fix
...d native_write_cr0(unsigned long val);
-fastcall unsigned int native_read_cr2(void);
-fastcall void native_write_cr2(unsigned int val);
+fastcall unsigned long native_read_cr2(void);
+fastcall void native_write_cr2(unsigned long val);
-fastcall unsigned int native_read_cr3(void);
-fastcall void native_write_cr3(unsigned int val);
+fastcall unsigned long native_read_cr3(void);
+fastcall void native_write_cr3(unsigned long val);
-fastcall unsigned int native_read_cr4(void);
-fastcall unsigned int native_read_cr4_safe(void);
-fastcall void native_write_cr4(unsigned int val);
+fastcall unsigned long native_...
2017 Oct 04
0
[PATCH 04/13] x86/paravirt: Convert DEF_NATIVE macro to GCC extended asm syntax
...+22,9 @@
#define NATIVE_RESTORE_FL "push " _REG_ARG1 "; popf"
#define NATIVE_IRQ_DISABLE "cli"
#define NATIVE_IRQ_ENABLE "sti"
-#define NATIVE_READ_CR2 "mov %cr2, " _REG_RET
-#define NATIVE_READ_CR3 "mov %cr3, " _REG_RET
-#define NATIVE_WRITE_CR3 "mov " _REG_ARG1 ", %cr3"
+#define NATIVE_READ_CR2 "mov %%cr2, " _REG_RET
+#define NATIVE_READ_CR3 "mov %%cr3, " _REG_RET
+#define NATIVE_WRITE_CR3 "mov " _REG_ARG1 ", %%cr3"
#define NATIVE_FLUSH_TLB_SINGLE "invlpg (" _RE...
2007 Apr 18
0
[RFC/PATCH PV_OPS X86_64 03/17] paravirt_ops - system routines
...ne void native_write_cr2(unsigned long val)
+{
+ asm volatile("movq %0,%%cr2": :"r" (val));
+}
+
+static inline unsigned long native_read_cr3(void)
+{
+ unsigned long val;
+ asm volatile("movq %%cr3,%0\n\t" :"=r" (val));
+ return val;
+}
+
+static inline void native_write_cr3(unsigned long val)
+{
+ asm volatile("movq %0,%%cr3": :"r" (val));
+}
+
+static inline unsigned long native_read_cr4(void)
+{
+ unsigned long val;
+ asm volatile("movq %%cr4,%0\n\t" :"=r" (val));
+ return val;
+}
+
+static inline void native_write_cr4(unsigne...
2007 Apr 18
0
[RFC/PATCH PV_OPS X86_64 03/17] paravirt_ops - system routines
...ne void native_write_cr2(unsigned long val)
+{
+ asm volatile("movq %0,%%cr2": :"r" (val));
+}
+
+static inline unsigned long native_read_cr3(void)
+{
+ unsigned long val;
+ asm volatile("movq %%cr3,%0\n\t" :"=r" (val));
+ return val;
+}
+
+static inline void native_write_cr3(unsigned long val)
+{
+ asm volatile("movq %0,%%cr3": :"r" (val));
+}
+
+static inline unsigned long native_read_cr4(void)
+{
+ unsigned long val;
+ asm volatile("movq %%cr4,%0\n\t" :"=r" (val));
+ return val;
+}
+
+static inline void native_write_cr4(unsigne...
2017 Oct 04
31
[PATCH 00/13] x86/paravirt: Make pv ops code generation more closely match reality
This changes the pv ops code generation to more closely match reality.
For example, instead of:
callq *0xffffffff81e3a400 (pv_irq_ops.save_fl)
vmlinux will now show:
pushfq
pop %rax
nop
nop
nop
nop
nop
which is what the runtime version of the code will show in most cases.
This idea was suggested by Andy Lutomirski.
The benefits are:
- For the most common runtime cases
2017 Oct 04
31
[PATCH 00/13] x86/paravirt: Make pv ops code generation more closely match reality
This changes the pv ops code generation to more closely match reality.
For example, instead of:
callq *0xffffffff81e3a400 (pv_irq_ops.save_fl)
vmlinux will now show:
pushfq
pop %rax
nop
nop
nop
nop
nop
which is what the runtime version of the code will show in most cases.
This idea was suggested by Andy Lutomirski.
The benefits are:
- For the most common runtime cases
2018 Aug 10
13
[PATCH 00/10] x86/paravirt: several cleanups
This series removes some no longer needed stuff from paravirt
infrastructure and puts large quantities of paravirt ops under a new
config option PARAVIRT_XXL which is selected by XEN_PV only.
A pvops kernel without XEN_PV being configured is about 2.5% smaller
with this series applied.
tip commit 5800dc5c19f34e6e03b5adab1282535cb102fafd ("x86/paravirt:
Fix spectre-v2 mitigations for
2018 Aug 10
0
[PATCH 04/10] x86/paravirt: use a single ops structure
...ident_32)
@@ -394,84 +308,162 @@ NOKPROBE_SYMBOL(native_load_idt);
#define PTE_IDENT __PV_IS_CALLEE_SAVE(_paravirt_ident_64)
#endif
-struct pv_mmu_ops pv_mmu_ops __ro_after_init = {
-
- .read_cr2 = native_read_cr2,
- .write_cr2 = native_write_cr2,
- .read_cr3 = __native_read_cr3,
- .write_cr3 = native_write_cr3,
-
- .flush_tlb_user = native_flush_tlb,
- .flush_tlb_kernel = native_flush_tlb_global,
- .flush_tlb_one_user = native_flush_tlb_one_user,
- .flush_tlb_others = native_flush_tlb_others,
-
- .pgd_alloc = __paravirt_pgd_alloc,
- .pgd_free = paravirt_nop,
+struct paravirt_patch_template pv_ops = {
+ /...
2017 Sep 04
0
[PATCH] x86/paravirt: remove no longer used paravirt functions
...void native_wbinvd(void)
extern asmlinkage void native_load_gs_index(unsigned);
+static inline unsigned long __read_cr4(void)
+{
+ return native_read_cr4();
+}
+
#ifdef CONFIG_PARAVIRT
#include <asm/paravirt.h>
#else
@@ -173,11 +178,6 @@ static inline void write_cr3(unsigned long x)
native_write_cr3(x);
}
-static inline unsigned long __read_cr4(void)
-{
- return native_read_cr4();
-}
-
static inline void __write_cr4(unsigned long x)
{
native_write_cr4(x);
diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c
index bc0a849589bb..0b338ec7e9d2 100644
--- a/arch/x86/kernel/pa...
2017 Sep 04
0
[PATCH] x86/paravirt: remove no longer used paravirt functions
...void native_wbinvd(void)
extern asmlinkage void native_load_gs_index(unsigned);
+static inline unsigned long __read_cr4(void)
+{
+ return native_read_cr4();
+}
+
#ifdef CONFIG_PARAVIRT
#include <asm/paravirt.h>
#else
@@ -173,11 +178,6 @@ static inline void write_cr3(unsigned long x)
native_write_cr3(x);
}
-static inline unsigned long __read_cr4(void)
-{
- return native_read_cr4();
-}
-
static inline void __write_cr4(unsigned long x)
{
native_write_cr4(x);
diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c
index bc0a849589bb..0b338ec7e9d2 100644
--- a/arch/x86/kernel/pa...
2018 Aug 13
11
[PATCH v2 00/11] x86/paravirt: several cleanups
This series removes some no longer needed stuff from paravirt
infrastructure and puts large quantities of paravirt ops under a new
config option PARAVIRT_XXL which is selected by XEN_PV only.
A pvops kernel without XEN_PV being configured is about 2.5% smaller
with this series applied.
tip commit 5800dc5c19f34e6e03b5adab1282535cb102fafd ("x86/paravirt:
Fix spectre-v2 mitigations for
2007 Dec 20
6
[PATCH 0/15] adjust pvops to accomodate its x86_64 variant
Hi folks,
With this series, the bulk of the work of pvops64 is done.
Here, I integrate most of the paravirt.c and paravirt.h files, making
them applicable to both architectures.
CONFIG_PARAVIRT is _not_ present yet. Basically, this code is missing page
table integration (patches currently being worked on by Jeremy).
Enjoy
2007 Dec 20
6
[PATCH 0/15] adjust pvops to accomodate its x86_64 variant
Hi folks,
With this series, the bulk of the work of pvops64 is done.
Here, I integrate most of the paravirt.c and paravirt.h files, making
them applicable to both architectures.
CONFIG_PARAVIRT is _not_ present yet. Basically, this code is missing page
table integration (patches currently being worked on by Jeremy).
Enjoy
2007 Oct 09
2
[PATCH RFC REPOST 1/2] paravirt: refactor struct paravirt_ops into smaller pv_*_ops
...- .cpuid = native_cpuid,
- .get_debugreg = native_get_debugreg,
- .set_debugreg = native_set_debugreg,
- .clts = native_clts,
- .read_cr0 = native_read_cr0,
- .write_cr0 = native_write_cr0,
- .read_cr2 = native_read_cr2,
- .write_cr2 = native_write_cr2,
- .read_cr3 = native_read_cr3,
- .write_cr3 = native_write_cr3,
- .read_cr4 = native_read_cr4,
- .read_cr4_safe = native_read_cr4_safe,
- .write_cr4 = native_write_cr4,
- .save_fl = native_save_fl,
- .restore_fl = native_restore_fl,
- .irq_disable = native_irq_disable,
- .irq_enable = native_irq_enable,
- .safe_halt = native_safe_halt,
- .halt = native_halt,
-...
2007 Oct 09
2
[PATCH RFC REPOST 1/2] paravirt: refactor struct paravirt_ops into smaller pv_*_ops
...- .cpuid = native_cpuid,
- .get_debugreg = native_get_debugreg,
- .set_debugreg = native_set_debugreg,
- .clts = native_clts,
- .read_cr0 = native_read_cr0,
- .write_cr0 = native_write_cr0,
- .read_cr2 = native_read_cr2,
- .write_cr2 = native_write_cr2,
- .read_cr3 = native_read_cr3,
- .write_cr3 = native_write_cr3,
- .read_cr4 = native_read_cr4,
- .read_cr4_safe = native_read_cr4_safe,
- .write_cr4 = native_write_cr4,
- .save_fl = native_save_fl,
- .restore_fl = native_restore_fl,
- .irq_disable = native_irq_disable,
- .irq_enable = native_irq_enable,
- .safe_halt = native_safe_halt,
- .halt = native_halt,
-...