search for: native_read_cr3

...SAVE_FL "pushf; pop " _REG_RET > +#define NATIVE_RESTORE_FL "push " _REG_ARG1 "; popf" > +#define NATIVE_IRQ_DISABLE "cli" > +#define NATIVE_IRQ_ENABLE "sti" > +#define NATIVE_READ_CR2 "mov %cr2, " _REG_RET > +#define NATIVE_READ_CR3 "mov %cr3, " _REG_RET > +#define NATIVE_WRITE_CR3 "mov " _REG_ARG1 ", %cr3" > +#define NATIVE_FLUSH_TLB_SINGLE "invlpg (" _REG_ARG1 ")" > +#define NATIVE_SWAPGS "swapgs" > +#define NATIVE_IRET "iret" > +#de...

..._REG_RET +#define NATIVE_SAVE_FL "pushf; pop " _REG_RET +#define NATIVE_RESTORE_FL "push " _REG_ARG1 "; popf" +#define NATIVE_IRQ_DISABLE "cli" +#define NATIVE_IRQ_ENABLE "sti" +#define NATIVE_READ_CR2 "mov %cr2, " _REG_RET +#define NATIVE_READ_CR3 "mov %cr3, " _REG_RET +#define NATIVE_WRITE_CR3 "mov " _REG_ARG1 ", %cr3" +#define NATIVE_FLUSH_TLB_SINGLE "invlpg (" _REG_ARG1 ")" +#define NATIVE_SWAPGS "swapgs" +#define NATIVE_IRET "iret" +#define NATIVE_QUEUED_SPIN_U...

...g native_read_cr0(void); +fastcall void native_write_cr0(unsigned long val); -fastcall unsigned int native_read_cr2(void); -fastcall void native_write_cr2(unsigned int val); +fastcall unsigned long native_read_cr2(void); +fastcall void native_write_cr2(unsigned long val); -fastcall unsigned int native_read_cr3(void); -fastcall void native_write_cr3(unsigned int val); +fastcall unsigned long native_read_cr3(void); +fastcall void native_write_cr3(unsigned long val); -fastcall unsigned int native_read_cr4(void); -fastcall unsigned int native_read_cr4_safe(void); -fastcall void native_write_cr4(unsigned in...

...g native_read_cr0(void); +fastcall void native_write_cr0(unsigned long val); -fastcall unsigned int native_read_cr2(void); -fastcall void native_write_cr2(unsigned int val); +fastcall unsigned long native_read_cr2(void); +fastcall void native_write_cr2(unsigned long val); -fastcall unsigned int native_read_cr3(void); -fastcall void native_write_cr3(unsigned int val); +fastcall unsigned long native_read_cr3(void); +fastcall void native_write_cr3(unsigned long val); -fastcall unsigned int native_read_cr4(void); -fastcall unsigned int native_read_cr4_safe(void); -fastcall void native_write_cr4(unsigned in...

...quot;mov " _REG_ARG1 ", " _REG_RET @@ -22,9 +22,9 @@ #define NATIVE_RESTORE_FL "push " _REG_ARG1 "; popf" #define NATIVE_IRQ_DISABLE "cli" #define NATIVE_IRQ_ENABLE "sti" -#define NATIVE_READ_CR2 "mov %cr2, " _REG_RET -#define NATIVE_READ_CR3 "mov %cr3, " _REG_RET -#define NATIVE_WRITE_CR3 "mov " _REG_ARG1 ", %cr3" +#define NATIVE_READ_CR2 "mov %%cr2, " _REG_RET +#define NATIVE_READ_CR3 "mov %%cr3, " _REG_RET +#define NATIVE_WRITE_CR3 "mov " _REG_ARG1 ", %%cr3&quot...

...ed long native_read_cr2(void) +{ + unsigned long val; + asm volatile("movq %%cr2,%0\n\t" :"=r" (val)); + return val; +} + +static inline void native_write_cr2(unsigned long val) +{ + asm volatile("movq %0,%%cr2": :"r" (val)); +} + +static inline unsigned long native_read_cr3(void) +{ + unsigned long val; + asm volatile("movq %%cr3,%0\n\t" :"=r" (val)); + return val; +} + +static inline void native_write_cr3(unsigned long val) +{ + asm volatile("movq %0,%%cr3": :"r" (val)); +} + +static inline unsigned long native_read_cr4(void) +...

...ed long native_read_cr2(void) +{ + unsigned long val; + asm volatile("movq %%cr2,%0\n\t" :"=r" (val)); + return val; +} + +static inline void native_write_cr2(unsigned long val) +{ + asm volatile("movq %0,%%cr2": :"r" (val)); +} + +static inline unsigned long native_read_cr3(void) +{ + unsigned long val; + asm volatile("movq %%cr3,%0\n\t" :"=r" (val)); + return val; +} + +static inline void native_write_cr3(unsigned long val) +{ + asm volatile("movq %0,%%cr3": :"r" (val)); +} + +static inline unsigned long native_read_cr4(void) +...

Hi, This patch series is an update of my previous paravirt_ops patches. They are loosely based on Ingo's original paravirt_ops implementation for KVM. Some of the changes since the last series include: 1) Switch to using CPUID 0x40000000 instead of using MSR writes to discover shared memory area 2) Attempt to deal with SMP guests 3) Support for generic CR read caching 4) Support for

Hi, This patch series is an update of my previous paravirt_ops patches. They are loosely based on Ingo's original paravirt_ops implementation for KVM. Some of the changes since the last series include: 1) Switch to using CPUID 0x40000000 instead of using MSR writes to discover shared memory area 2) Attempt to deal with SMP guests 3) Support for generic CR read caching 4) Support for

This changes the pv ops code generation to more closely match reality. For example, instead of: callq *0xffffffff81e3a400 (pv_irq_ops.save_fl) vmlinux will now show: pushfq pop %rax nop nop nop nop nop which is what the runtime version of the code will show in most cases. This idea was suggested by Andy Lutomirski. The benefits are: - For the most common runtime cases

This changes the pv ops code generation to more closely match reality. For example, instead of: callq *0xffffffff81e3a400 (pv_irq_ops.save_fl) vmlinux will now show: pushfq pop %rax nop nop nop nop nop which is what the runtime version of the code will show in most cases. This idea was suggested by Andy Lutomirski. The benefits are: - For the most common runtime cases

Hi folks, With this series, the bulk of the work of pvops64 is done. Here, I integrate most of the paravirt.c and paravirt.h files, making them applicable to both architectures. CONFIG_PARAVIRT is _not_ present yet. Basically, this code is missing page table integration (patches currently being worked on by Jeremy). Enjoy

Hi folks, With this series, the bulk of the work of pvops64 is done. Here, I integrate most of the paravirt.c and paravirt.h files, making them applicable to both architectures. CONFIG_PARAVIRT is _not_ present yet. Basically, this code is missing page table integration (patches currently being worked on by Jeremy). Enjoy

....init_IRQ = native_init_IRQ, - - .cpuid = native_cpuid, - .get_debugreg = native_get_debugreg, - .set_debugreg = native_set_debugreg, - .clts = native_clts, - .read_cr0 = native_read_cr0, - .write_cr0 = native_write_cr0, - .read_cr2 = native_read_cr2, - .write_cr2 = native_write_cr2, - .read_cr3 = native_read_cr3, - .write_cr3 = native_write_cr3, - .read_cr4 = native_read_cr4, - .read_cr4_safe = native_read_cr4_safe, - .write_cr4 = native_write_cr4, - .save_fl = native_save_fl, - .restore_fl = native_restore_fl, - .irq_disable = native_irq_disable, - .irq_enable = native_irq_enable, - .safe_halt = native_sa...

....init_IRQ = native_init_IRQ, - - .cpuid = native_cpuid, - .get_debugreg = native_get_debugreg, - .set_debugreg = native_set_debugreg, - .clts = native_clts, - .read_cr0 = native_read_cr0, - .write_cr0 = native_write_cr0, - .read_cr2 = native_read_cr2, - .write_cr2 = native_write_cr2, - .read_cr3 = native_read_cr3, - .write_cr3 = native_write_cr3, - .read_cr4 = native_read_cr4, - .read_cr4_safe = native_read_cr4_safe, - .write_cr4 = native_write_cr4, - .save_fl = native_save_fl, - .restore_fl = native_restore_fl, - .irq_disable = native_irq_disable, - .irq_enable = native_irq_enable, - .safe_halt = native_sa...

....init_IRQ = native_init_IRQ, - - .cpuid = native_cpuid, - .get_debugreg = native_get_debugreg, - .set_debugreg = native_set_debugreg, - .clts = native_clts, - .read_cr0 = native_read_cr0, - .write_cr0 = native_write_cr0, - .read_cr2 = native_read_cr2, - .write_cr2 = native_write_cr2, - .read_cr3 = native_read_cr3, - .write_cr3 = native_write_cr3, - .read_cr4 = native_read_cr4, - .read_cr4_safe = native_read_cr4_safe, - .write_cr4 = native_write_cr4, - .save_fl = native_save_fl, - .restore_fl = native_restore_fl, - .irq_disable = native_irq_disable, - .irq_enable = native_irq_enable, - .safe_halt = native_sa...

....init_IRQ = native_init_IRQ, - - .cpuid = native_cpuid, - .get_debugreg = native_get_debugreg, - .set_debugreg = native_set_debugreg, - .clts = native_clts, - .read_cr0 = native_read_cr0, - .write_cr0 = native_write_cr0, - .read_cr2 = native_read_cr2, - .write_cr2 = native_write_cr2, - .read_cr3 = native_read_cr3, - .write_cr3 = native_write_cr3, - .read_cr4 = native_read_cr4, - .read_cr4_safe = native_read_cr4_safe, - .write_cr4 = native_write_cr4, - .save_fl = native_save_fl, - .restore_fl = native_restore_fl, - .irq_disable = native_irq_disable, - .irq_enable = native_irq_enable, - .safe_halt = native_sa...

....init_IRQ = native_init_IRQ, - - .cpuid = native_cpuid, - .get_debugreg = native_get_debugreg, - .set_debugreg = native_set_debugreg, - .clts = native_clts, - .read_cr0 = native_read_cr0, - .write_cr0 = native_write_cr0, - .read_cr2 = native_read_cr2, - .write_cr2 = native_write_cr2, - .read_cr3 = native_read_cr3, - .write_cr3 = native_write_cr3, - .read_cr4 = native_read_cr4, - .read_cr4_safe = native_read_cr4_safe, - .write_cr4 = native_write_cr4, - .save_fl = native_save_fl, - .restore_fl = native_restore_fl, - .irq_disable = native_irq_disable, - .irq_enable = native_irq_enable, - .safe_halt = native_sa...

....init_IRQ = native_init_IRQ, - - .cpuid = native_cpuid, - .get_debugreg = native_get_debugreg, - .set_debugreg = native_set_debugreg, - .clts = native_clts, - .read_cr0 = native_read_cr0, - .write_cr0 = native_write_cr0, - .read_cr2 = native_read_cr2, - .write_cr2 = native_write_cr2, - .read_cr3 = native_read_cr3, - .write_cr3 = native_write_cr3, - .read_cr4 = native_read_cr4, - .read_cr4_safe = native_read_cr4_safe, - .write_cr4 = native_write_cr4, - .save_fl = native_save_fl, - .restore_fl = native_restore_fl, - .irq_disable = native_irq_disable, - .irq_enable = native_irq_enable, - .safe_halt = native_sa...

...+static unsigned long native_read_cr2(void) +{ + unsigned long val; + asm volatile("movq %%cr2,%0\n\t" :"=r" (val)); + return val; +} + +static void native_write_cr2(unsigned long val) +{ + asm volatile("movq %0,%%cr2": :"r" (val)); +} + +static unsigned long native_read_cr3(void) +{ + unsigned long val; + asm volatile("movq %%cr3,%0\n\t" :"=r" (val)); + return val; +} + +static void native_write_cr3(unsigned long val) +{ + asm volatile("movq %0,%%cr3": :"r" (val)); +} + +static unsigned long native_read_cr4(void) +{ + unsigned l...