Displaying 3 results from an estimated 3 matches for "napll".
2020 May 29
2
[PATCH] drm/nouveau/clk/gm20b: Fix memory leak in gm20b_clk_new
...b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
@@ -1039,7 +1039,7 @@ gm20b_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
ret = gk20a_clk_ctor(device, index, &gm20b_clk, clk_params,
&clk->base);
if (ret)
- return ret;
+ goto out_free;
/*
* NAPLL can only work with max_u, clamp the m range so
@@ -1067,8 +1067,8 @@ gm20b_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
nvkm_warn(subdev, "no fused calibration parameters\n");
ret = gm20b_clk_init_safe_fmax(clk);
- if (ret)
- return ret;
- return 0;
+ou...
2020 May 31
0
[PATCH] drm/nouveau/clk/gm20b: Fix memory leak in gm20b_clk_new
...vice, int index, struct nvkm_clk **pclk)
> ret = gk20a_clk_ctor(device, index, &gm20b_clk, clk_params,
> &clk->base);
> if (ret)
> - return ret;
> + goto out_free;
>
> /*
> * NAPLL can only work with max_u, clamp the m range so
> @@ -1067,8 +1067,8 @@ gm20b_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
> nvkm_warn(subdev, "no fused calibration parameters\n");
>
> ret = gm20b_clk_init_safe_fmax(clk);
> -...
2016 Jun 01
15
[PATCH 00/15] clk/tegra: improve code and add DFS support
This series adds support for GM20B PLL's Maxwell features, namely glitchless
switch and (more importantly) DFS support. DFS lets the PLL lower its output
speed according to input current variations, making the clock more stable and
allowing it to run safely at lower voltage.
All GM20B additions are done in the last patch, which consequently ends up
being considerably big ; fortunately, it