search for: namespacellvm_1_1isd

...sponds to a record. For example, TableGen has a class Register, and your backend will define records by def GPR8 : Register<...>. You are correct in saying that the record definition is one of the SDNode values. These correspond 1:1 to llvm::ISD::NodeType <http://llvm.org/docs/doxygen/html/namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110> . (DEF a, b) corresponds to --------- a / DEF \ ----------b A more complicated example, regarding that a and b themselves can be nested DAGs. a / --------- add / \ /...

Matt, Is this an example you are talking about: LoadedVect = DAG.getNode <http://llvm.org/docs/doxygen/html/classllvm_1_1SelectionDAG.html#ab02868bea897db34232413f1929ade1d> (ISD::INTRINSIC_WO_CHAIN <http://llvm.org/docs/doxygen/html/namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac771b9cda3b889242d457cc4d9b2159c>, dl, MVT::v4f64, DAG.getConstant <http://llvm.org/docs/doxygen/html/classllvm_1_1SelectionDAG.html#adf7343dcb7fff67cf516abca4c1d6793>(Intrinsic::ppc_qpx_qvfcfidu, dl, MVT::i32), LoadedVect); Something like...

On Fri, Jan 29, 2016 at 11:39 AM, Rail Shafigulin <rail at esenciatech.com> wrote: > > > On Thu, Jan 28, 2016 at 8:34 PM, Dylan McKay <dylanmckay34 at gmail.com> > wrote: > >> Try visualising the DAG like this. >> >> ``` >> ---- GPR:$rA >> / >> set GPR:$rd ---- add >>

...re handler there. The stack area at ???? seems to be used to store callee-saved register and something else. I don't know how to get the correct ???? though. Should I take a look on `FRAME_TO_ARGS_OFFSET` [1], or there is another way to achieve what I want? Thanks. [1] http://llvm.org/doxygen/namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a228deacdfba1bd2d5a3663b19609f945 ​ ​ ​ ​Regards, chenwj​ -- Wei-Ren Chen (陳韋任) Homepage: https://people.cs.nctu.edu.tw/~chenwj -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/att...

Matt, Thanks for the response. Is there an example in the code somewhere of doing the intrinsic ID method? I don't need to put it a lot of places so I'm not sure it warrants adding a node. Thanks. On Tue, Feb 2, 2016 at 12:35 PM, Matt Arsenault <arsenm2 at gmail.com> wrote: > > > On Feb 2, 2016, at 09:29, Ryan Taylor via llvm-dev < > llvm-dev at lists.llvm.org>

...t; wrote: > > Matt, > > Is this an example you are talking about: > > LoadedVect = DAG.getNode > <http://llvm.org/docs/doxygen/html/classllvm_1_1SelectionDAG.html#ab02868bea897db34232413f1929ade1d> > (ISD::INTRINSIC_WO_CHAIN > <http://llvm.org/docs/doxygen/html/namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac771b9cda3b889242d457cc4d9b2159c>, > dl, MVT::v4f64, > DAG.getConstant > <http://llvm.org/docs/doxygen/html/classllvm_1_1SelectionDAG.html#adf7343dcb7fff67cf516abca4c1d6793>(Intrinsic::ppc_qpx_qvfcfidu, > dl, MVT::i32), > Load...

> However, fp-contract is not a knob to control whether or not abstract-machine operations generate a single arithmetic instruction I think that makes sense, but the end result is the same. Wouldn't you agree that -fp-contract=off still contracts floating point expressions with the initial example I posted? That is the core of what I'm trying to resolve here. I still have some

On Thu, Jan 28, 2016 at 8:34 PM, Dylan McKay <dylanmckay34 at gmail.com> wrote: > Try visualising the DAG like this. > > ``` > ---- GPR:$rA > / > set GPR:$rd ---- add > \ > ---- GPR:$rB > ``` > > Each instruction forms a DAG with its operands being subnodes. > >

I probably misunderstood the question. You probably want to do this in SelectionDAG. On Fri, Oct 21, 2016 at 10:29 AM, Ehsan Amiri <ehsanamiri at gmail.com> wrote: > You can do this by changing instruction scheduling heuristics. I think the > more important question is if this correct always for all platforms. > > I don't know which scheduler you use. We use