search for: nagurne

Displaying 6 results from an estimated 6 matches for "nagurne".

2020 Sep 09
2
[EXTERNAL] RE: Machinepipeliner interface. shouldIgnoreForPipelining, actually not ignoring.
Hi James, One last thing - is your target upstream? or are you working on a downstream target? Cheers, James On Tue, 8 Sep 2020 at 23:02, Nagurne, James <j-nagurne at ti.com> wrote: > I greatly appreciate you going back to gather that intel, James. It > actually helps my understanding of the whole pipeliner puzzle quite a bit! > > > > I did identify, like you, that the MachinePipeliner pass (more precisely, > Swin...
2020 Sep 07
2
[EXTERNAL] RE: Machinepipeliner interface. shouldIgnoreForPipelining, actually not ignoring.
...est against upstream, but the personpower required wasn't available. As always, it was with the best of intentions, and I do think that the cleanup of MachinePipeliner was worth it (the PeelingScheduleExpander is much easier to reason about, IMHO). Cheers, James On Thu, 3 Sep 2020 at 20:41, Nagurne, James <j-nagurne at ti.com> wrote: > We have that behaves similarly to yours in this regard it seems. > Specifically, our target utilizes the HardwareLoop pass with CounterInReg > true, and then treats loops augmented by this pass as software pipeline > candidates. It seems PPC...
2020 Sep 03
1
[EXTERNAL] RE: Machinepipeliner interface. shouldIgnoreForPipelining, actually not ignoring.
...unroll / peel the prolog epilog anyway. Targets like Hexagon or PPC with dedicated loop control instructions for pipelined loops don't need this, but our target was simple RISC. It was for that reason that I felt the feature would be useful for other targets. James On Thu, 3 Sep 2020, 17:19 Nagurne, James, <j-nagurne at ti.com> wrote: > Ah, I apologize for not seeing the meaning of your first email. I had not > considered that he was working on an out-of-tree target that utilizes the > ignore capability. You’ve made things very clear, thank you! > > > > Since he’s...
2020 Sep 02
2
[EXTERNAL] Re: Machinepipeliner interface. shouldIgnoreForPipelining, actually not ignoring.
...to allow the target to strip those instructions from the pipelined kernel.” However, the reality is that the implementation seems incomplete and there’s no instructions on how to achieve the desired result. Is it left as an exercise to the reader/implementer? Is there something I’m missing? J.B. Nagurne Code Generation Texas Instruments From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of Jinsong Ji via llvm-dev Sent: Tuesday, June 2, 2020 2:58 PM To: Sander Cc: llvm-dev at lists.llvm.org Subject: [EXTERNAL] Re: [llvm-dev] Machinepipeliner interface. shouldIgnoreForPipelining,...
2020 Aug 07
2
Branches which return values in SelectionDAG
...ave ideas, I just didn't want to fill this email with debug. Is what I'm doing possible? Or does it make sense to keep the special and separate compare_and_maybe_decrement operation until after selection is finished so that I can fuse using MachineInstrs instead? Thanks for any help! J.B. Nagurne Code Generation Texas Instruments -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20200807/5ebc2826/attachment.html>
2020 Jun 01
2
Machinepipeliner interface. shouldIgnoreForPipelining, actually not ignoring.
Hi all, I think there is a mistake in the machinepipeliner interface. In the TargetInstrInfo.h in the class PipelinerLoopInfo there is a function "bool shouldIgnoreForPipelining(const MachineInstr *MI)". The description says that if this function returns true for a given MachineInstr it will not be pipelined. However in reality it is not ignored and is being considered for