search for: nagaraju

On Wed, Apr 22, 2020 at 10:34 PM David Blaikie <dblaikie at gmail.com> wrote: > > > > On Wed, Apr 22, 2020 at 9:28 AM Nagaraju Mekala via llvm-dev <llvm-dev at lists.llvm.org> wrote: >> >> On Tue, Apr 21, 2020 at 6:16 PM Robinson, Paul <paul.robinson at sony.com> wrote: >> > >> > >> > >> > > -----Original Message----- >> > > From: llvm-dev <llvm-...

On Tue, Apr 21, 2020 at 6:16 PM Robinson, Paul <paul.robinson at sony.com> wrote: > > > > > -----Original Message----- > > From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Nagaraju > > Mekala via llvm-dev > > Sent: Tuesday, April 21, 2020 6:04 AM > > To: jh7370.2008 at my.bristol.ac.uk > > Cc: LLVM Developers Mailing List <llvm-dev at lists.llvm.org> > > Subject: Re: [llvm-dev] Debug symbols are missing in elf > > > > Hi James,...

...et which requires to generated two instructions for a single branch instruction. ex: imm 1 br r4,0xabcd branch address is 0x1abcd, imm has the upper 16 bits and br has lower 16 bits. Can anyone let me know how to write these kind of patterns in the InstrInfo.td file. Thanks in Advance, Nagaraju

...ision of splitting later in the pipeling during MC lowering. Decision about when you need to split should be driven by your intent to do any further processing over constituent instruction. ~ Jatin On Fri, Mar 2, 2018 at 8:19 PM, Jatin Bhateja <jatin.bhateja at gmail.com> wrote: > Hi Nagaraju, > > Few suggestions split this into following steps. > > 1/ DAG Legalization : Custom lower the instruction (branch in your case) > appropriately in legalization to target specific DAG nodes and glue the > nodes together which you want scheduler should schedule together. > &gt...

...showing those warning messages and continued to generate disassembly without .debug sections init. > But yeah, don't really know what's happening there. Might be you need to debug the linker & see what it's reading/being confused by. > > On Sat, Apr 18, 2020 at 10:05 AM Nagaraju Mekala <nagaraju.mekala87 at gmail.com> wrote: >> >> >> >> On Saturday, April 18, 2020, David Blaikie <dblaikie at gmail.com> wrote: >>> >>> >>> >>> On Sat, Apr 18, 2020 at 3:02 AM Nagaraju Mekala via llvm-dev <llvm-dev at l...

...byte block: 51 (DW_OP_reg1 (r1)) <31> DW_AT_name : (indirect string, offset: 0x0): clang version 8.0.1 <35> DW_AT_decl_file : 1 <36> DW_AT_decl_line : 51 <37> DW_AT_type : <0x66> <3b> DW_AT_external : 1 -Nagaraju On Mon, Apr 20, 2020 at 1:26 PM James Henderson <jh7370.2008 at my.bristol.ac.uk> wrote: > > It looks to me like the DWARF is corrupt somehow. What happens if you try using llvm-objdump (as opposed to a GNU-based objdump) to dump the information? What warning(s) do you see? That'll...

Hi Florian, Thanks for the reply. On Fri, Dec 8, 2017 at 6:48 PM, Florian Hahn <florian.hahn at arm.com> wrote: > Hi, > > On 08/12/2017 06:24, Nagaraju Mekala via llvm-dev wrote: >> >> Hi all, >> >> I am new to LLVM. Currently working on adding an embedded target to >> LLVM backend. >> I was able to generate the object file for our target using LLVM and >> Clang framework. >> The generated o...

Hi Nagaraju, Few suggestions split this into following steps. 1/ DAG Legalization : Custom lower the instruction (branch in your case) appropriately in legalization to target specific DAG nodes and glue the nodes together which you want scheduler should schedule together. 2/ Instruction Selection : Define p...

On Fri, Mar 2, 2018 at 4:59 PM, David Chisnall <David.Chisnall at cl.cam.ac.uk> wrote: > On 2 Mar 2018, at 11:09, Nagaraju Mekala via llvm-dev <llvm-dev at lists.llvm.org> wrote: >> >> I am working on a target which requires to generated two >> instructions for a single branch instruction. >> ex: >> imm 1 >> br r4,0xabcd >> branch address is 0x1abcd, imm has the u...

On Saturday, April 18, 2020, David Blaikie <dblaikie at gmail.com> wrote: > > > On Sat, Apr 18, 2020 at 3:02 AM Nagaraju Mekala via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> Hello All, >> >> I was trying to add Microblaze target to LLVM backend. I was able to >> generate object file with relocations. and debug symbols. >> >> When I try to link this object fi...

...framework. The generated object file doesn't contain any debug symbols in it. I tried searching documents related to this on web but couldn't find any. Can anyone please point some links/documents on generation of dwarf debug symbols for the generated object file. Thanks in Advance Nagaraju

On 2 Mar 2018, at 11:45, Nagaraju Mekala <nagaraju.mekala87 at gmail.com> wrote: > > yes they are dependent if the branch immediate value is > 0xffff then > the imm instruction should generate other wise only "br" instruction > is enough. This sounds as if you have two br instructions, one that take...

On 2 Mar 2018, at 11:09, Nagaraju Mekala via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > I am working on a target which requires to generated two > instructions for a single branch instruction. > ex: > imm 1 > br r4,0xabcd > branch address is 0x1abcd, imm has the upper 16 bits and br has &gt...

...24 swi r3, r1, 36 80000248: e8a10028 lwi r5, r1, 40 8000024c: f8610020 swi r3, r1, 32 80000250: 10650000 addk r3, r5, r0 80000254: b60f0008 rtsd r15, 8 80000258: 80000000 or r0, r0, r0 Thanks in Advance, Nagaraju

...k3 which was deployed in vmware esxi to oVirt by using "v2v" tool ,imported successfully after powering on unable to get the login prompt getting stuck at "windows is starting". can someone help me in this issue ? pls help me to know the commands to get the virt2v logs Thanks, Nagaraju