Displaying 4 results from an estimated 4 matches for "naelr8".
2015 May 20
2
[LLVMdev] Implement a Register Allocator in LLVM
I'm working on my project for completion undergraduate courses, consisting
of an experimental analysis of registers allocation algorithms. For this
task, I am using the set of tools from the LLVM project.
However, I have read the documentation of the LLVM project and not yet
found a way to put the pieces of the puzzle together. So far I know:
- As passes work as engage them to LLVM and
2015 Sep 04
2
LiveInterval and Loop Info
Thanks Matthias
I can also use the method intervalIsInOneMBB() from LiveIntervals class to
relate a LiveInterval to a MachineBasicBlock, right?
Em 04/09/2015 2:26 PM, "Matthias Braun" <mbraun at apple.com> escreveu:
> There is no direct support for this, but you can use
> LiveIntervalAnalysis::getMBBStartIndex()/getMBBEndIndex()/getMBBFromIndex()
> to relate the
2015 Jul 09
3
[LLVMdev] PHI Elimination in Register Allocation Pass
Good Afternoon.
I am a Computer Science undergraduate student in Brazil and as completion
of course work, I am developing an register allocator, using the
infrastructure of the LLVM.
To accomplish this task, I have based my implementation in allocators
already implemented in LLVM. But a question came to me while I was
researching in books and articles of compiler theory and own documentation
of
2015 Nov 19
2
Build a Interference Graph
Ok, just to clarify, RegUnits, as far I understand, are Physical registers
or alias to Physical registers. They exist because some instructions use
physical registers directly rather than virtual register. It's right?
And why this RegUnits should be present in the Interference Graph? I
thought were only the Live Intervals would be the nodes of the graph.
Sorry about the trouble to