search for: nadav

Displaying 20 results from an estimated 928 matches for "nadav".

2012 Oct 08
3
[LLVMdev] LLVM Loop Vectorizer (Nadav Rotem)
On 10/08/2012 06:02 AM, Nadav Rotem wrote: > Hi Javed, > > Developing a good loop vectorizer takes several years. The work on the GCC vectorizer began in 2004, and they spent several years improving and optimizing their vectorizer. They started by vectorizing simple loops, and added features that they needed in order...
2016 Nov 06
10
Vectorizers code ownership
...these discussions I recommend Michael Kuperstein. Michael is committed to improving LLVM and has lots of relevant experience. If approved by the community, I know he would do a great job working with contributors on improving the vectorizers and reviewing the recent proposals from ARM and Intel. -Nadav -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20161106/8d3738a6/attachment.html>
2011 Dec 06
2
[LLVMdev] [llvm-commits] Vectors of Pointers and Vector-GEP
Hi, I just wanted to let you know that I committed the pointer-vector patch. Thanks, Nadav -----Original Message----- From: David A. Greene [mailto:greened at obbligato.org] Sent: Tuesday, December 06, 2011 00:10 To: Jose Fonseca Cc: David A. Greene; Rotem, Nadav; LLVM Developers Mailing List Subject: Re: [LLVMdev] [llvm-commits] Vectors of Pointers and Vector-GEP Jose Fonseca <jf...
2013 Oct 21
2
[LLVMdev] Bug #16941
Nadav, You are absolutely right, it's ISPC workload. I've checked SSE4 and it's also severely affected. We use intrinsics only for conversion <N x i32> <=> i32, i.e. movmsk.ps. For the rest we use general LLVM instructions. And I actually would really like to stick this way. We...
2012 Apr 15
2
[LLVMdev] [llvm-commits] Vectors of Pointers and Vector-GEP
.../gather using a vector of pointers/indices. For example AVX2 has support for the 'gather' instruction which receives a vector of indices. In many cases it is possible to lower vector-gep instructions into a gather instruction, but this is currently not supported by LLVM. Thanks, Nadav -----Original Message----- From: Hal Finkel [mailto:hfinkel at anl.gov] Sent: Saturday, April 14, 2012 11:02 To: Rotem, Nadav Cc: David A. Greene; Jose Fonseca; LLVM Developers Mailing List Subject: Re: [LLVMdev] [llvm-commits] Vectors of Pointers and Vector-GEP On Tue, 6 Dec 2011 09:19:43 +0...
2012 Apr 14
0
[LLVMdev] [llvm-commits] Vectors of Pointers and Vector-GEP
On Tue, 6 Dec 2011 09:19:43 +0200 "Rotem, Nadav" <nadav.rotem at intel.com> wrote: > Hi, > > I just wanted to let you know that I committed the pointer-vector > patch. Nadav, I just committed a change to BBVectorizer to allow it to generate these (and also vector selects) [>= r154735]. If you have cases where you...
2011 Nov 29
4
[LLVMdev] [llvm-commits] Vectors of Pointers and Vector-GEP
----- Original Message ----- > "Rotem, Nadav" <nadav.rotem at intel.com> writes: > > > David, > > > > Thanks for the support! I sent a detailed email with the overall > > plan. But just to reiterate, the GEP would look like this: > > > > %PV = getelementptr <4 x i32*> %base, <4 x i3...
2012 Oct 07
4
[LLVMdev] LLVM Loop Vectorizer (Nadav Rotem)
Hi Nadav (and others who are related to this issue) - I saw some discussions on loop vectorizer that you are planning to write. Do you foresee using Polyhedral Framework (polly project) in some way in that. Thanks J. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http:...
2012 Feb 27
2
[LLVMdev] llvm-stress for fuzzing llvm
...truction triggered the bug is often not enough. I use bugpoint to reduce the failing test. The reason is that some of the bugs may be caused by the interaction between several instruction. Having said that, I think that the change that you proposed is a good one. Can you send a patch ? Thanks, Nadav From: Sean Silva [mailto:silvas at purdue.edu] Sent: Monday, February 27, 2012 05:45 To: Hal Finkel Cc: Rotem, Nadav; llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] llvm-stress for fuzzing llvm I'm finding it useful to replace the main loop with:   for (unsigned i = 0, n = SizeCL/Modifie...
2012 Oct 08
0
[LLVMdev] LLVM Loop Vectorizer (Nadav Rotem)
...king on a general loop-vectorizer design. I think that any design that we choose must take Polly into consideration. But I don't think that we need to start with loops that require polyhedral optimizer. I think that we should start with the examples from the gcc vectorizer page[1]. Thanks, Nadav [1] - http://gcc.gnu.org/projects/tree-ssa/vectorization.html First, we need to check and see if Polly is the solution to the problems that we have. On Oct 7, 2012, at 8:50 AM, Javed Absar <javed.absar at gmail.com> wrote: > Hi Nadav (and others who are rel...
2013 Jul 27
1
[LLVMdev] [llvm] r187267 - SLP Vectorier: Don't vectorize really short chains because they are already handled by the SelectionDAG store-vectorizer, which does a better job in deciding when to vectorize.
Hi Nadav, Okay. 1. The comment doesn't make this clear. I would suggest, at a minimum, updating it to mention pairs specifically, to avoid the issue in #2 2. If the day comes when the selectiondag store vectorizer handles more than pairs, and does so better, is anyone really going to remember this ra...
2012 Feb 26
4
[LLVMdev] llvm-stress for fuzzing llvm
...to be used by the random function. I implemented a simple portable 'random' function so that the result should be identical on all platforms. The initial seed also appears in the name of the generated function. The "-size" parameter sets the size of the generated random file. Nadav --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended...
2019 May 17
2
[PATCH v4 0/4] vmw_balloon: Compaction and shrinker support
> On May 3, 2019, at 6:25 PM, Nadav Amit <namit at vmware.com> wrote: > >> On Apr 25, 2019, at 4:54 AM, Nadav Amit <namit at vmware.com> wrote: >> >> VMware balloon enhancements: adding support for memory compaction, >> memory shrinker (to prevent OOM) and splitting of refused pages to >&gt...
2019 May 17
2
[PATCH v4 0/4] vmw_balloon: Compaction and shrinker support
> On May 3, 2019, at 6:25 PM, Nadav Amit <namit at vmware.com> wrote: > >> On Apr 25, 2019, at 4:54 AM, Nadav Amit <namit at vmware.com> wrote: >> >> VMware balloon enhancements: adding support for memory compaction, >> memory shrinker (to prevent OOM) and splitting of refused pages to >&gt...
2013 Oct 21
0
[LLVMdev] Bug #16941
...ions. The SEXT to i32 pattern was implemented because LLVM did not support vector-selects when this code was written. Can you submit a small SSE4 test case that demonstrates the problem? Select is the canonical form of this operations, and SEXT is usually more difficult to lower. Thanks, Nadav On Oct 21, 2013, at 11:12 AM, Dmitry Babokin <babokin at gmail.com> wrote: > Nadav, > > You are absolutely right, it's ISPC workload. I've checked SSE4 and it's also severely affected. > > We use intrinsics only for conversion <N x i32> <=> i32, i.e....
2011 Dec 10
2
[LLVMdev] [cfe-dev] GEP index type
...he information that the index is a 32-bit value. If I had this information then I would have been able to use the AVX2 instruction in many cases. Do you see a way to overcome this problem ? Since InstCombiner has this optimization, can we talk about dropping this optimization in clang ? Thanks, Nadav -----Original Message----- From: Eli Friedman [mailto:eli.friedman at gmail.com] Sent: Saturday, December 10, 2011 23:48 To: Rotem, Nadav Cc: cfe-dev at cs.uiuc.edu Developers Subject: Re: [cfe-dev] GEP index type On Sat, Dec 10, 2011 at 9:20 AM, Rotem, Nadav <nadav.rotem at intel.com>...
2012 Feb 27
0
[LLVMdev] llvm-stress for fuzzing llvm
Here is that patch. Btw, I've just been using bugpoint, and it's really nifty! --Sean Silva 2012/2/27 Rotem, Nadav <nadav.rotem at intel.com> > Sean, > > Thanks for looking at this. Knowing that the last instruction triggered > the bug is often not enough. I use bugpoint to reduce the failing test. > The reason is that some of the bugs may be caused by the interaction > between sever...
2016 Nov 09
3
Vectorizers code ownership
...last few years. I think that Craig Topper would be a great code owner, assuming he wants to be. Craig, an Intel employee, has been working on the X86 backend for years. He implemented most of the AVX2 support, worked on performance improvements and worked with Elena on AVX512. What do you think? -Nadav On Nov 08, 2016, at 04:25 PM, Quentin Colombet <qcolombet at apple.com> wrote: Hi Nadav, What about your code ownership on the X86 backend? Simon Pilgrim, Sanjay Patel, and a few others have been very active on that backend if you are looking for a replacement. Cheers, -Quentin On Nov 5,...
2013 Jul 27
2
[LLVMdev] [llvm] r187267 - SLP Vectorier: Don't vectorize really short chains because they are already handled by the SelectionDAG store-vectorizer, which does a better job in deciding when to vectorize.
Hey Nadav, I'd humbly suggest that rather than use 3 directly, you should add a shared constant between these two passes, so when one changes, the other doesn't need to be updated. It would also ensure this bit of info about what needs to be updated isn't only contained in the comments.. On Fri,...
2011 Jul 30
3
[LLVMdev] "Cannot select" error in 2.9
Gregory Junker wrote: >>> -----Original Message----- >>> From: Rotem, Nadav [mailto:nadav.rotem at intel.com] >>> Sent: Saturday, July 30, 2011 6:51 AM >>> To: Gregory Junker >>> Subject: RE: [LLVMdev] "Cannot select" error in 2.9 >>> >>> Can you reduce the test with bug-point ? Does it work on ToT ? >> >>...