search for: n_lo

...ou cannot however. Alexandre Courbot (15): volt/gk20a: split constructor volt: add GM20B driver clk/gk20a: convert parameters to Khz clk/gk20a: reorganize variables in gk20a_pllg_calc_mnp() clk/gk20a: rename enable/disable functions clk/gk20a: fix VCO bit mask clk/gk20a: only compute n_lo if needed clk/gk20a: only restore divider to 1:1 if needed clk/gk20a: emit parent rate as debug message clk/gk20a: put mnp values into their own struct clk/gk20a: abstract pl_to_div clk/gk20a: split gk20a_clk_new() clk/gk20a: set lowest frequency during init() clk/gk20a: share reusabl...

...v, GPCPLL_CFG); +} + +static void +_gk20a_pllg_disable(struct gk20a_clock_priv *priv) +{ + nv_mask(priv, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0); + nv_rd32(priv, GPCPLL_CFG); +} + +static int +_gk20a_pllg_program_mnp(struct gk20a_clock_priv *priv, bool allow_slide) +{ + u32 val, cfg; + u32 m_old, pl_old, n_lo; + + /* get old coefficients */ + val = nv_rd32(priv, GPCPLL_COEFF); + m_old = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); + pl_old = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); + + /* do NDIV slide if there is no change in M and PL */ + cfg = nv_...

...able(struct gk20a_clock_priv *priv) > +{ > + nv_mask(priv, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0); > + nv_rd32(priv, GPCPLL_CFG); > +} > + > +static int > +_gk20a_pllg_program_mnp(struct gk20a_clock_priv *priv, bool allow_slide) > +{ > + u32 val, cfg; > + u32 m_old, pl_old, n_lo; > + > + /* get old coefficients */ > + val = nv_rd32(priv, GPCPLL_COEFF); > + m_old = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); > + pl_old = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); > + > + /* do NDIV slide if there is n...

This series adds support for reclocking on GK20A. The first two patches touch the clock subsystem to allow GK20A to operate, by making the presence of the thermal and voltage devices optional, and allowing pstates to be provided directly instead of being probed using the BIOS (which Tegra does not have). The last patch adds the GK20A clock device. Arguably the clock can be seen as a stripped-down

...parameter clk/gk20a: properly protect macro argument clk/gk20a: setup slide once during init clk/gk20a: reorganize MNP calculation a bit clk/gk20a: use nvkm_ functions in slide() clk/gk20a: add and use MNP programming functions clk/gk20a: parameterize PLL settings clk/gk20a: factorize n_lo computation code clk/gk20a: improve MNP programming clk/gk20a: rename constructor clk/gm20b: add glitchless and DFS support drm/nouveau/include/nvkm/core/tegra.h | 1 + drm/nouveau/nvkm/engine/device/tegra.c | 1 + drm/nouveau/nvkm/subdev/clk/gk20a.c | 394 +++++++-------- drm/nouve...

Second version of the gk20a clock patches. I have tried to keep the therm and volt devices mandatory in the clock driver, but unfortunately they are too tied to bios to allow this, at least for the moment. Consequently this version is mostly a port of the first version to Ben's tree. Ben, please let me know what I have done wrong in terms of integration to your tree, as the main purpose of

...ds on IA64 */ #define acpi_processor_cstate_check(x) (x) /* no idle limits on IA64 :) */ static inline void disable_acpi(void) { } --- a/xen/include/asm-x86/acpi.h +++ b/xen/include/asm-x86/acpi.h @@ -79,8 +79,7 @@ int __acpi_release_global_lock(unsigned :"0"(n_hi), "1"(n_lo)) extern bool_t acpi_lapic, acpi_ioapic, acpi_noirq; -extern bool_t acpi_force, acpi_ht; -extern bool_t acpi_disabled, acpi_pci_disabled; +extern bool_t acpi_force, acpi_ht, acpi_disabled; extern bool_t acpi_skip_timer_override; extern u32 acpi_smi_cmd; extern u8 acpi_enable_value, acpi_disab...