search for: n32

https://bugzilla.mindrot.org/show_bug.cgi?id=2590 Bug ID: 2590 Summary: Seccomp filter for missing architectures Product: Portable OpenSSH Version: 7.2p1 Hardware: Other OS: Linux Status: NEW Keywords: patch Severity: enhancement Priority: P5 Component: sshd

...sor.h> +#include <asm/uaccess.h> +#include <xen/public/privcmd.h> + +int privcmd_ioctl_32(int fd, unsigned int cmd, unsigned long arg) +{ + int ret; + + switch (cmd) { + case IOCTL_PRIVCMD_MMAP_32: { + struct privcmd_mmap *p; + struct privcmd_mmap_32 *p32; + struct privcmd_mmap_32 n32; + + p32 = compat_ptr(arg); + p = compat_alloc_user_space(sizeof(*p)); + if (copy_from_user(&n32, p32, sizeof(n32)) || + put_user(n32.num, &p->num) || + put_user(n32.dom, &p->dom) || + put_user(compat_ptr(n32.entry), &p->entry)) + return -EFAULT; + +...

...Daniel.Sanders at imgtec.com> wrote: > Hi, > > Having recently enabled IAS by default for the MIPS O32 ABI, I'm now trying to do the same thing for the MIPS N64 ABI. Unfortunately, it is not currently possible to enable IAS by default for the N64 ABI without also enabling it for the N32 ABI because this information is not reflected in the triple and that's the only information MipsMCAsmInfo has. What would it take to pass more information to MipsMCAsmInfo? > For MIPS, I'm defining Triple::GNUABI32, Triple::GNUABIN32, and Triple::GNUABI64. All three of these are suppor...

...alayout for R600. This may seem like a bold move, but I think it is warranted. R600/SI is a strange architecture in that it uses 64bit pointers but does not support 64 bit arithmetic except for load/store operations that roughly map onto getelementptr. The current datalayout for r600 includes n32:64, which is odd because r600 cannot actually do any 64bit arith natively. This causes particular problems in the optimizer with the following kernel: __kernel void if_eq(__global unsigned long* out, unsigned arg0) { int i=0; for(i = 0; i < arg0; i++){ out[i] = i; }...

Hi, Having recently enabled IAS by default for the MIPS O32 ABI, I'm now trying to do the same thing for the MIPS N64 ABI. Unfortunately, it is not currently possible to enable IAS by default for the N64 ABI without also enabling it for the N32 ABI because this information is not reflected in the triple and that's the only information MipsMCAsmInfo has. This would be fine if it N32 was also in a good state but the current N32 ABI support for IAS is badly broken and will likely take considerable effort to fix (and fixing it also requir...

..., Yu Rong Tan On Mon, Jun 16, 2014 at 5:30 PM, Matheus Almeida <Matheus.Almeida at imgtec.com> wrote: > Could you be more specific about what ABIs are you after ? The reason I'm asking is that there are several ABIs available for Mips and only a few of them are supported by LLVM (o32, n32 and n64). There are several ABIs defined by GNU with very little documentation that describes them (EABI is one example). > > We are aware that the available documentation and GCC disagree sometimes and given that GCC is the de-facto standard, LLVM tries to follow GCC's behaviour as close...

...roduce an O32 binary given a combination of O32+fpxx, and similarly a O32+fp64 binary given a combination O32+fpxx and O32+fp64. > Interesting. I'd seen some of the discussion, but not read it in any detail. >> Curious why an extension to o32 for this and not, for example, just using n32? > > N32 is an ABI that requires 64-bit general purpose registers so it's not supportable on a 32-bit ISA. More importantly, it would be difficult (if not impossible) to arrange that downstream source bases transition all their code to a new ABI at once. The seamless migration from O32 to...

...r the -mips32 test-suite (there's no FPU or local disk on this machine so some tests take a very long time). > > clang+llvm-3.5.1-rc2-x86_64-linux-gnu-ubuntu-14.04.tar.xz (cross-compiling to Mips): > All ok for all ISA's more recent than mips32, all ABI's except big-endian N32*, and both endians. > > * I seem to have mis-stated the results for rc1 for the big-endian N32 ABI, sorry. It fails 12 tests (previously I stated 'all ok' but looking at those log files again, this was incorrect) and the failing tests seem to involve pointers passed in varargs. This...

...plemented a long time ago and I can only guess at this point but I'd say that there were some misinterpretations of the spec and given the popularity of GCC, the implementation became the new standard and it's something that LLVM needs to cope with. > There are a lot of MIPS ABIs. o32, n32, n64 - These came from the SGI world for IRIX originally, but were also adopted for linux and used in gcc for both. o64 - Invented at Cygnus for 64-bit processors eabi - Different one invented at Cygnus meabi - Invented with MIPS and Cygnus (and possibly others) in the late 90s as a new embedded ab...

...em in a va_list, then printing each one) for all ABI's/endians and mixtures of GCC/Clang. > > I've also run the first 5,000 ABITestGen.py generated tests for all ABI's/Endians. Big-endian O32 shows a single failure involving small structures (this is not a regression). Big-endian N32 shows about a dozen failures that do not fail on the trunk but aren't regressions either. All other ABI's and Endians are passing successfully. Even with those big-endian N32 failures (which fail without the patches too), this status is a big improvement on the status without the patches so...

...1 on the upper 32-bits of a double precision value is not permitted. > * Some callee-saved registers are also treated as caller-saved. > Well, this is definitely ABI breaking, so effectively a new ABI is what I meant. Curious why an extension to o32 for this and not, for example, just using n32? -eric >> -----Original Message----- >> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] >> On Behalf Of Eric Christopher >> Sent: 18 June 2014 18:48 >> To: Matheus Almeida >> Cc: LLVM Developers Mailing List >> Subject: Re: [L...

Full_Name: George N. White III Version: 1.9.0 OS: Irix 6.5.21m Submission from: (NULL) (142.176.61.212) R-1.9.0 built using the SGI MIPSPro compilers Installation directory: /usr/local C compiler: c99 -OPT:IEEE_NaN_inf=ON -mips4 -n32 -O3 -OPT:Olimit_opt=on C++ compiler: CC -OPT:IEEE_NaN_inf=ON -mips4 -n32 -O3 -OPT:Olimit_opt=on -LANG:std Fortran compiler: f90 -OPT:IEEE_NaN_inf=ON -mips4 -n32 -O3 -OPT:Olimit_opt=on Interfaces supported: X11, gnome, tcltk External libraries: readline, BL...

...t; wrote: > > Hi, > > > > Having recently enabled IAS by default for the MIPS O32 ABI, I'm now > trying to do the same thing for the MIPS N64 ABI. Unfortunately, it is not > currently possible to enable IAS by default for the N64 ABI without also > enabling it for the N32 ABI because this information is not reflected in the > triple and that's the only information MipsMCAsmInfo has. > > What would it take to pass more information to MipsMCAsmInfo? All callers of createMCAsmInfo() and LLVMCreateDisasmCPUFeatures() would need to specify the ABI. In the...

...en –mabi is not given but they may differ when –mabi is given. As I mentioned above, I'm trying to do a very similar thing to r224492 but I have an additional problem to deal with. In my scenario, clang doesn't start off with a triple that clearly specifies the ABI (mips64-linux-gnu can be N32 or N64 depending on –mabi) which makes it impossible for the bits of LLVM that can't see MCTargetOptions to know what to do. I therefore start by normalizing the triple in clang to one that does specify the ABI clearly and is consistent with the –mabi option. With that problem solved, the rest...

But then I should write // CHECK: something // SSE: something // SSE3: something With this feature it can be write // {{[A-Z0-9]+}} : something From: James Y Knight [mailto:jyknight at google.com] Sent: Thursday, May 26, 2016 5:53 PM To: Ehsan Amiri <ehsanamiri at gmail.com> Cc: Elena Lepilkina <Elena.Lepilkina at synopsys.com>; llvm-dev <llvm-dev at lists.llvm.org> Subject:

> > > > I'd also like to propose the inclusion of the recent ABI fixes to the Mips > > > > target but I'm not sure this is a good idea. I'm having difficulty sorting out the > > > > dependencies for these at the moment since they seem to depend on some > > > > of Eric Christopher's Subtarget/TargetMachine refactoring. It may also be a

Hi Matheus, Thank you for your information! Do you known where do download MIPS ABI/EABI document? Thanks in advance! -- Best Regards, Yu Rong Tan On Thu, Jun 12, 2014 at 7:14 PM, Matheus Almeida <Matheus.Almeida at imgtec.com> wrote: > An assembler is the tool you're after. [And a linker if you want to have an executable in the end]. > > You can specify -filetype=obj to

On Thu, May 26, 2016 at 10:35 AM, Ehsan Amiri via llvm-dev < llvm-dev at lists.llvm.org> wrote: > 7. Wildcard for prefixes - If some statements should be checked > regardless prefix, it should be used //{{*}}, //{{*}}-NEXT, //{{*}}-SAME > and etc. > >> 8. Prefix with regular expressions - If statement should be >> checked if prefix matches some regular

In "Writing an LLVM Compiler Backend", there's some discussion of the TargetDescription string, but it doesn't explain the examples I look at. For instance, in the description of the PowerPC, I see "E-p:64:64-f64:64:64-i64:64:64-f128:64:128-n32:64" What's "preferred alignment" versus "ABI alignment"? What are the 3 figures following the "i"? (the documentation suggests there will only be 2). I see two entries for "f". Do I read these as info about "f64" and "f128"?...

...the MC layer. ABI Let's start at ExecuteAssembler() in cc1as_main.cpp. Here's a sketch of what happens: * Call TargetRegistry::lookupTarget() to get a llvm::Target. * Call createMCRegInfo(Triple, ...) * Call createMCAsmInfo(..., Triple) * MipsMCAsmInfo::PointerSize is incorrect for the N32 ABI (should be 4 but gets 8 since it checks for Triple::mips64/mips64el) * MipsMCAsmInfo::CalleeSaveStackSlotSize is incorrect for mips-linux-gnu –mips64 –mabi=64. Since it too checks for Triple::mips64/mips64el * MipsMCAsmInfo::PrivateLabelPrefix and MipsMCAsmInfo::PrivateGlobalPrefix are wron...