Displaying 3 results from an estimated 3 matches for "mywritemulvector".
2018 Nov 17
2
Per-write cycle count with ReadAdvance - Do I really need that?
...ctor
> register. There are different latencies since forwarding/bypass appears. I
> give it as below example:
>
> def : WriteRes<WriteVector, [MyArchVALU]> { let Latency = 6; }
> ...
> def MyWriteAddVector : SchedWriteRes<[MyArchVALU]> { let Latency = 6; }
> def MyWriteMulVector : SchedWriteRes<[MyArchVALU]> { let Latency = 6; }
> ...
>
> Here I defined 3 different Writes with same latency number. Below shows
> the forwarding.
>
> def : ReadAdvance<MyReadVector, 5, [WriteVector]>;
> def : ReadAdvance<MyReadVector, 3, [MyWriteAddVector_3c...
2018 Nov 19
2
Per-write cycle count with ReadAdvance - Do I really need that?
...escribe that .
>
>
> Does this work for you?
>
> // Forward from a vector op (normal, add, mul) to a non-store.
> def : ReadAdvance<MyReadVector, 5, [WriteVector]>;
> def : ReadAdvance<MyReadVector, 3, [MyWriteAddVector]>;
> def : ReadAdvance<MyReadVector, 1, [MyWriteMulVector]>;
>
> A ReadAdvance is associated with a pair of write resource -> read
> resource. You can specify as many variants of read/write resources as you
> want, even using arbitrary C++ code inside a predicate. So, in theory I
> think that should be flexible enough.
>
> You c...
2018 Nov 15
2
Per-write cycle count with ReadAdvance - Do I really need that?
...describes reading my ARCH's vector
register. There are different latencies since forwarding/bypass appears. I
give it as below example:
def : WriteRes<WriteVector, [MyArchVALU]> { let Latency = 6; }
...
def MyWriteAddVector : SchedWriteRes<[MyArchVALU]> { let Latency = 6; }
def MyWriteMulVector : SchedWriteRes<[MyArchVALU]> { let Latency = 6; }
...
Here I defined 3 different Writes with same latency number. Below shows the
forwarding.
def : ReadAdvance<MyReadVector, 5, [WriteVector]>;
def : ReadAdvance<MyReadVector, 3, [MyWriteAddVector_3cycles]>;
def : ReadAdvance<...