search for: mywriteaddvector

It does not work. I have tried to use the latest master today. But tblgen still give me information like error: Resources are defined for both SchedRead and its alias on processor MyArchModel def : ReadAdvance<MyReadVector, 3, [MyWriteAddVector]>; ^ Unless I change "MyReadVector" to another read like "MyReadVector1", it would not work. Debugging into tblgen, there is no path to handle multiplle latencies for same Read... Anyway as you reminded, I am searching for more Target and am looking into Pierre's change...

.... > > It is about the scheduler info which describes reading my ARCH's vector > register. There are different latencies since forwarding/bypass appears. I > give it as below example: > > def : WriteRes<WriteVector, [MyArchVALU]> { let Latency = 6; } > ... > def MyWriteAddVector : SchedWriteRes<[MyArchVALU]> { let Latency = 6; } > def MyWriteMulVector : SchedWriteRes<[MyArchVALU]> { let Latency = 6; } > ... > > Here I defined 3 different Writes with same latency number. Below shows > the forwarding. > > def : ReadAdvance<MyReadVector, 5,...

...adAdvance feature to work with my ARCH. It is about the scheduler info which describes reading my ARCH's vector register. There are different latencies since forwarding/bypass appears. I give it as below example: def : WriteRes<WriteVector, [MyArchVALU]> { let Latency = 6; } ... def MyWriteAddVector : SchedWriteRes<[MyArchVALU]> { let Latency = 6; } def MyWriteMulVector : SchedWriteRes<[MyArchVALU]> { let Latency = 6; } ... Here I defined 3 different Writes with same latency number. Below shows the forwarding. def : ReadAdvance<MyReadVector, 5, [WriteVector]>; def : ReadAdv...