Displaying 2 results from an estimated 2 matches for "mytargetschedule".
2017 Apr 03
2
Scheduler: modelling long register reservations?
...writes the FXLV's result register---including instructions which overwrite only one lane of the vector result. Am I specifying the scheduling constraints incorrectly? Can llvm support this kind of constraint?
Thank you,
Nick Johnson
D. E. Shaw Research
// Excerpted from lib/Target/MyTarget/MyTargetSchedule.td:
//
def DesGCv3GenericModel : SchedMachineModel
{
let IssueWidth = 1;
let MicroOpBufferSize = 0;
let CompleteModel = 1;
}
// ...
def FlexU : ProcResource<64> { let BufferSize = 1; }
def : WriteRes<IIFlexRead, [FlexU]> { let Latency = 25; let ResourceCycles =...
2015 Oct 15
3
what can cause a "CPU table is not sorted" assertion
I'm trying to create a simplified 2 slot VLIW from an OR1K. The codebase
I'm working with is here <https://github.com/openrisc/llvm-or1k>. I've
created an initial MyTargetSchedule.td
def MyTargetModel : SchedMachineModel {
// HW can decode 2 instructions per cycle.
let IssueWidth = 2;
let LoadLatency = 4;
let MispredictPenalty = 16;
// This flag is set to allow the scheduler to assign a default model to
// unrecognized opcodes.
let CompleteModel = 0;
}
def W...