Displaying 6 results from an estimated 6 matches for "mytargetregisterinfo".
2009 Mar 30
1
[LLVMdev] Dear Evan Chang, Re: help: about how to use tblgen to constraint operand.
...Reg = 1066
12494 VReg RegClass size = 8, align = 8
12495 Expected RegClass size = 8, align = 8
12496 Fatal error, aborting.
12497 0 llc 0x08bbc5cb
12498 1 llc 0x08bbc93c
12499 2 0x00110400 __kernel_sigreturn + 0
++++++++++++++++++++++++++++
I define register class in mytargetRegisterInfo.td. In here, I binding all
register class with supported variable type.
I believe leaf node--Register is band with virtual register number at Initial DAG.
But I do not know why LLC use my GPR64 register to save f64 type variable?
I want to know where pass or function llc binding type with regist...
2019 May 28
2
Instruction is selected, but it shouldn't (?)
In MyTargetRegisterInfo.td file, I defined separated register classes for general purpose registers and for the SP register:
def GR16 : RegisterClass<"CPU74", [i16], 16, (add R0, R1, R2, R3, R4, R5, R6, R7)>;
def SSP : RegisterClass<"CPU74", [i16], 16, (add SP)>;
The SP can not be used in...
2009 Feb 20
2
[LLVMdev] help: about how to use tblgen to constraint operand.
hi, Dear Evan Cheng:
My cpu is i32 embeded CPU. I define pseudo register pair registers.
In mytargetRegisterInfo.td:
def T0: RegisterWithSubRegs<"t0",[R0,R1]>;
...
def GPR64 : RegisterClass<"mytarget", [i64], 64, [T0, T1.....]
In mytargetISelLowering.cpp:
I define i1, i8 , i16 and i32 are legal.
1. I still have problem. I save my function return double value in R0 and R1.
It...
2009 Mar 31
1
[LLVMdev] 转发: Re: Dear Evan Chang, Re: help: about how to use tblgen to constraint operand.
...eg = 1066
12494 VReg RegClass size = 8, align = 8
12495 Expected RegClass size = 8, align = 8
12496 Fatal error, aborting.
12497 0
llc 0x08bbc5cb
12498 1 llc 0x08bbc93c
12499 2 0x00110400 __kernel_sigreturn + 0
++++++++++++++++++++++++++++
I define register class in mytargetRegisterInfo.td. In here, I binding all
register class with supported variable type.
I believe leaf node--Register is band with virtual register number at Initial DAG.
But I do not know why LLC use my GPR64 register to save f64 type variable?
I want to know where pass or function llc binding type with regist...
2009 Feb 20
0
[LLVMdev] help: about how to use tblgen to constraint operand.
On Feb 19, 2009, at 8:26 PM, 任坤 wrote:
> hi, Dear Evan Cheng:
>
> My cpu is i32 embeded CPU. I define pseudo register pair registers.
>
> In mytargetRegisterInfo.td:
> def T0: RegisterWithSubRegs<"t0",[R0,R1]>;
> ...
> def GPR64 : RegisterClass<"mytarget", [i64], 64, [T0, T1.....]
>
> In mytargetISelLowering.cpp:
> I define i1, i8 , i16 and i32 are legal.
>
> 1. I still have problem. I save my function re...
2019 May 28
2
Instruction is selected, but it shouldn't (?)
...t;
> From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Joan Lluch via llvm-dev
> Sent: Tuesday, May 28, 2019 11:31 AM
> To: via llvm-dev <llvm-dev at lists.llvm.org>
> Subject: [EXT] [llvm-dev] Instruction is selected, but it shouldn't (?)
>
> In MyTargetRegisterInfo.td file, I defined separated register classes for general purpose registers and for the SP register:
>
> def GR16 : RegisterClass<"CPU74", [i16], 16, (add R0, R1, R2, R3, R4, R5, R6, R7)>;
> def SSP : RegisterClass<"CPU74", [i16], 16, (add SP)>;
>
>...