Displaying 6 results from an estimated 6 matches for "mytargetpassconfig".
2015 Nov 18
2
Hexagon, DFAPacketizer and instruction expansion
...gets
expanded into a write to a register and a jump/branch). I'm wondering if
Hexagon is experiencing the same issue and how it is solved? And if it
doesn't experience the same what would be the recommendation on solving
this problem? At the moment, my packetization pass is the last one in
MyTargetPassConfig::addPreEmitPass()
Any help is appreciated.
--
R
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2012 Mar 29
0
[LLVMdev] VLIWPacketizerList: failing to schedule terminators
...tructions must be correctly handled by the DAG builder. DAG edges will be built for all instructions within the block.
---
Now, regarding bundle creation. The FinalizeMachineBundles pass will "finalize" bundles for you after regalloc. You can enable that in your target config. e.g.
bool MyTargetPassConfig::addFinalizeRegAlloc() {
addPass(FinalizeMachineBundlesID);
}
This does not create bundles, rather it wraps bundles in an extra layer of abstraction by copying all of the MachineOperands into a bundle header. I think we have enough other bundle abstractions that this step could be eliminated,...
2012 Mar 29
2
[LLVMdev] VLIWPacketizerList: failing to schedule terminators
On Thu, Mar 29, 2012 at 02:57:27PM -0500, Sergei Larin wrote:
> Tom,
>
> I do not have your call stack, but packetizer calls
> ScheduleDAGInstrs::buildSchedGraph to create dependency model. If this is
> the first time you use the new MI sched infrastructure (like your target has
> not implemented misched yet) there might be some work needed to implement
> couple target
2015 Nov 19
2
Hexagon, DFAPacketizer and instruction expansion
...ister and a jump/branch). I'm wondering if
>> Hexagon is experiencing the same issue and how it is solved? And if it
>> doesn't experience the same what would be the recommendation on solving
>> this problem? At the moment, my packetization pass is the last one in
>> MyTargetPassConfig::addPreEmitPass()
>>
>
> There is a target-independent pass that will try to expand all pseudo
> instructions after register allocation. For each instruction, it will
> check if the instructions is a pseudo-instruction, and if so, it will call
> the target hook "expandPos...
2012 Mar 30
1
[LLVMdev] VLIWPacketizerList: failing to schedule terminators
...ly handled by the DAG builder. DAG edges will be built for all instructions within the block.
>
> ---
> Now, regarding bundle creation. The FinalizeMachineBundles pass will "finalize" bundles for you after regalloc. You can enable that in your target config. e.g.
>
> bool MyTargetPassConfig::addFinalizeRegAlloc() {
> addPass(FinalizeMachineBundlesID);
> }
>
> This does not create bundles, rather it wraps bundles in an extra layer of abstraction by copying all of the MachineOperands into a bundle header. I think we have enough other bundle abstractions that this step c...
2014 Jul 14
3
[LLVMdev] Register Machine Pass
It's not being executed. I'm both trying to print via outs() and add info
via STATISTIC, neither is occurring.
On Mon, Jul 14, 2014 at 12:22 PM, Justin Holewinski <jholewinski at nvidia.com>
wrote:
> On Mon, 2014-07-14 at 08:31 -0700, Ryan Taylor wrote:
> > Where is the documentation about registering a machine pass? I'm
> > unable to find it.
> >
>