Displaying 2 results from an estimated 2 matches for "mytargetmodel".
2015 Oct 15
3
what can cause a "CPU table is not sorted" assertion
I'm trying to create a simplified 2 slot VLIW from an OR1K. The codebase
I'm working with is here <https://github.com/openrisc/llvm-or1k>. I've
created an initial MyTargetSchedule.td
def MyTargetModel : SchedMachineModel {
// HW can decode 2 instructions per cycle.
let IssueWidth = 2;
let LoadLatency = 4;
let MispredictPenalty = 16;
// This flag is set to allow the scheduler to assign a default model to
// unrecognized opcodes.
let CompleteModel = 0;
}
def WriteALU : SchedWrite;...
2015 Nov 16
3
DFAPacketizer, Scheduling and LoadLatency
...;RI, [InstrStage<1, [Slot0, Slot1]>]>,
InstrItinData<LD, [InstrStage<1, [Slot0, Slot1]>]>, // <-- This
itinerary class describes load instructions
InstrItinData<BR, [InstrStage<1, [Slot0]>]>
..............................
]>;
def MyTargetModel : SchedMachineModel {
// Max issue per cycle == bundle width.
let IssueWidth = 2;
let Itineraries = MyTargetItineraries;
let LoadLatency = 2;
}
Nowhere in my itinerary description it says that load instruction takes 2
cycles. In the code I couldn't find a path (but I could have missed)...