Displaying 6 results from an estimated 6 matches for "mytargetisellow".
2009 Feb 20
2
[LLVMdev] help: about how to use tblgen to constraint operand.
hi, Dear Evan Cheng:
My cpu is i32 embeded CPU. I define pseudo register pair registers.
In mytargetRegisterInfo.td:
def T0: RegisterWithSubRegs<"t0",[R0,R1]>;
...
def GPR64 : RegisterClass<"mytarget", [i64], 64, [T0, T1.....]
In mytargetISelLowering.cpp:
I define i1, i8 , i16 and i32 are legal.
1. I still have problem. I save my function return double value in R0 and R1.
It is expanded into two i32. But my GPR64 is defined to save i64. llvm finds
I have i64 GPR register. It will automatically decide not to expand i64 to two i32.
2....
2009 Feb 19
1
[LLVMdev] help: about how to use tblgen to constraint operand.
...<0, f64>, SDTCisVT<1, i32>,
SDTCisSameAs<1, 2>]>;
def my_fmdrr : ...........
def myFMDRR : ....
(outs FPR: $result), ins(GPR: $op1, GPR:$op2 )
[(setFPR: $result, (my_fmdrr GPR: $op1, GPR:$op2) )]
I create myfmdrr instructure in mytargetISelLowering.cpp. and its operands are in R0 and R1.
But after optimization, the operands are save R2 and R1. I know optimization pass does not
know myfmdrr operands constraint. But How I tell optimzition pass by tblgen??
Could I can control operand constraint in mytargetiSelLowering.cpp? How do I contro...
2009 Feb 20
0
[LLVMdev] help: about how to use tblgen to constraint operand.
...Dear Evan Cheng:
>
> My cpu is i32 embeded CPU. I define pseudo register pair registers.
>
> In mytargetRegisterInfo.td:
> def T0: RegisterWithSubRegs<"t0",[R0,R1]>;
> ...
> def GPR64 : RegisterClass<"mytarget", [i64], 64, [T0, T1.....]
>
> In mytargetISelLowering.cpp:
> I define i1, i8 , i16 and i32 are legal.
>
> 1. I still have problem. I save my function return double value in
> R0 and R1.
> It is expanded into two i32. But my GPR64 is defined to save i64.
> llvm finds
> I have i64 GPR register. It will automatically decide...
2009 Mar 30
1
[LLVMdev] Dear Evan Chang, Re: help: about how to use tblgen to constraint operand.
...n Feb 19, 2009, at 8:26 PM, 任坤 wrote:
hi, Dear Evan Cheng:
My cpu is i32 embeded CPU. I define pseudo register pair registers.
In mytargetRegisterInfo.td:
def T0: RegisterWithSubRegs<"t0",[R0,R1]>;
...
def GPR64 : RegisterClass<"mytarget", [i64], 64, [T0, T1.....]
In mytargetISelLowering.cpp:
I define i1, i8 , i16 and i32 are legal.
1. I still have problem. I save my function return double value in R0 and R1.
It is expanded into two i32. But my GPR64 is defined to save i64. llvm finds
I have i64 GPR register. It will automatically decide not to expand i64 to two i32.
2....
2009 Mar 31
1
[LLVMdev] 转发: Re: Dear Evan Chang, Re: help: about how to use tblgen to constraint operand.
...Feb 19, 2009, at 8:26 PM, 任坤 wrote:
hi, Dear Evan Cheng:
My cpu is i32 embeded CPU. I define pseudo register
pair registers.
In mytargetRegisterInfo.td:
def T0: RegisterWithSubRegs<"t0",[R0,R1]>;
...
def GPR64 : RegisterClass<"mytarget", [i64], 64, [T0, T1.....]
In mytargetISelLowering.cpp:
I define i1, i8 , i16 and i32 are legal.
1. I still have problem. I save my function return double value in R0 and R1.
It is expanded into two i32. But my GPR64 is defined to save i64. llvm finds
I have i64 GPR register. It will automatically decide not to expand i64 to two i32.
2....
2015 Dec 30
2
Substitute instruction with a jump to a library code
I'm trying to find a way to emulate a floating point instruction, say a
floating point add. My understanding is that in order to do that I need to
execute
setOperationAction(ISD::FADD, (MVT::f32, Expand);
setOperationAction(ISD::FADD, (MVT::f64, Expand);
in MyTargetISelLowering.cpp, MyTargetLowering::MyTargetLowering(...).
However for some reason I'm still seeing a floating point add in the final
assembly. I tried running my test code (provided below) on MSP430 and can
see it execute a jump instruction to a label that is clearly located in the
library code.
Her...