Displaying 7 results from an estimated 7 matches for "mytargetdagtodagisel".
2016 Mar 30
2
Instruction selection pattern for intrinsic returning llvm_any_ty
...ction the call is lowered to
t6: i16,i16 = llvm.phx.divm.u16 TargetConstant:i16<3778>, t2, t4
which fits nicely to my divm16_pseudo that I want to select.
Is there any way I can select this with a tablegen pattern, and not
having to do selection "manually" in my target's
MytargetDAGToDAGISel::Select function?
I'm having a bunch of intrisics looking like this and I'd prefer
selecting them with patterns rather than doing much more verbose stuff
in C++.
I've tried to look in in-tree targets for something similar but I've
failed to find anything.
Thanks,
Mikael
2016 Mar 30
0
Instruction selection pattern for intrinsic returning llvm_any_ty
...to
>
> t6: i16,i16 = llvm.phx.divm.u16 TargetConstant:i16<3778>, t2, t4
>
> which fits nicely to my divm16_pseudo that I want to select.
>
> Is there any way I can select this with a tablegen pattern, and not having to do selection "manually" in my target's MytargetDAGToDAGISel::Select function?
>
> I'm having a bunch of intrisics looking like this and I'd prefer selecting them with patterns rather than doing much more verbose stuff in C++.
>
> I've tried to look in in-tree targets for something similar but I've failed to find anything.
>...
2014 Oct 29
2
[LLVMdev] Virtual register def doesn't dominate all uses
Hi Quentin,
yes, this happens quite late. With the Option --debug-pass=Structure it's in or after "Assembly Printer".
I do have a very simple DAGToDAGISel::Select() method:
SDNode *MyTargetDAGToDAGISel::Select(SDNode *N)
{
SDLoc dl(N);
// default implementation
if (N -> isMachineOpcode()) {
N -> setNodeId(-1);
return NULL; // Already selected.
}
SDNode *res = SelectCode(N);
return res;
}
Is that too simple? There are no further passes that eliminate anything.
Anywa...
2014 Oct 31
2
[LLVMdev] Virtual register def doesn't dominate all uses
...s Boesler <baembel at gmx.de> wrote:
>
>> Hi Quentin,
>>
>> yes, this happens quite late. With the Option --debug-pass=Structure it's in or after "Assembly Printer".
>> I do have a very simple DAGToDAGISel::Select() method:
>>
>> SDNode *MyTargetDAGToDAGISel::Select(SDNode *N)
>> {
>> SDLoc dl(N);
>> // default implementation
>> if (N -> isMachineOpcode()) {
>> N -> setNodeId(-1);
>> return NULL; // Already selected.
>> }
>> SDNode *res = SelectCode(N);
>> return res;
>> }
>>...
2016 Mar 30
2
Instruction selection pattern for intrinsic returning llvm_any_ty
...t6: i16,i16 = llvm.phx.divm.u16 TargetConstant:i16<3778>, t2, t4
>>
>> which fits nicely to my divm16_pseudo that I want to select.
>>
>> Is there any way I can select this with a tablegen pattern, and not having to do selection "manually" in my target's MytargetDAGToDAGISel::Select function?
>>
>> I'm having a bunch of intrisics looking like this and I'd prefer selecting them with patterns rather than doing much more verbose stuff in C++.
>>
>> I've tried to look in in-tree targets for something similar but I've failed to find a...
2014 Nov 01
2
[LLVMdev] Virtual register def doesn't dominate all uses
...>>>> Hi Quentin,
>>>>
>>>> yes, this happens quite late. With the Option --debug-pass=Structure it's in or after "Assembly Printer".
>>>> I do have a very simple DAGToDAGISel::Select() method:
>>>>
>>>> SDNode *MyTargetDAGToDAGISel::Select(SDNode *N)
>>>> {
>>>> SDLoc dl(N);
>>>> // default implementation
>>>> if (N -> isMachineOpcode()) {
>>>> N -> setNodeId(-1);
>>>> return NULL; // Already selected.
>>>> }
>>>> SDNode *r...
2014 Oct 24
2
[LLVMdev] Virtual register def doesn't dominate all uses
Hi!
During my backend development I get the error message for some tests:
*** Bad machine code: Virtual register def doesn't dominate all uses. ***
(C source-code, byte-code disassembly and printed machine code at the end of the email)
The first USE of vreg4 in BB#1 has no previous DEF in BB#0 or #1. But why? I can't see how the LLVM byte-code is transformed to the lower machine code.