Displaying 3 results from an estimated 3 matches for "myschedregistry".
2013 May 09
0
[LLVMdev] Scheduling with RAW hazards
...s MyScheduler : public MachineSchedStrategy {...}
namespace llvm {
ScheduleDAGInstrs *createMySched(MachineSchedContext *C) {
ScheduleDAGMI *DAG = new ScheduleDAGMI(C, new MyScheduler());
DAG->addMutation(new MyDAGMutation());
return DAG;
}
} // namespace llvm
static MachineSchedRegistry
MySchedRegistry("mysched", "Custom My scheduler.", createMySched);
-Andy
> Thanks,
> Fraser
>
> --
> Fraser Cormack
> Compiler Developer
> Codeplay Software Ltd
> 45 York Place, Edinburgh, EH1 3HP
> Tel: 0131 466 0503
> Fax: 0131 557 6600
> Website: http://w...
2013 May 13
1
[LLVMdev] Scheduling with RAW hazards
...;
> namespace llvm {
> ScheduleDAGInstrs *createMySched(MachineSchedContext *C) {
> ScheduleDAGMI *DAG = new ScheduleDAGMI(C, new MyScheduler());
> DAG->addMutation(new MyDAGMutation());
> return DAG;
> }
> } // namespace llvm
>
> static MachineSchedRegistry
> MySchedRegistry("mysched", "Custom My scheduler.", createMySched);
>
> -Andy
>
I've had a quick experiment with the MI Scheduler, and have a few
further questions. From what I can see, if I pass -enable-misched to the
compiler, it only works above O1, though addOptimizedRegAlloc...
2013 May 09
2
[LLVMdev] Scheduling with RAW hazards
I have an instruction that takes no operands, and produces two results,
in two consecutive cycles.
I tried both of the following to my Schedule.td file:
InstrItinData<IIMyInstr, [InstrStage<2, [FuncU]>], [1, 2]>,
InstrItinData<IIMyInstr, [InstrStage<1, [FuncU]>, InstrStage<1,
[FuncU]>], [1, 2]>,
From what I can see in examples, these say that the first