Displaying 2 results from an estimated 2 matches for "myregisterclass".
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mcregisterclass
2016 Sep 24
2
RFC: Implement variable-sized register classes
On 9/24/2016 7:20 AM, Alex Bradbury wrote:
> My concern is that all of the above adds yet more complexity to what
> is already (in my view) a fairly difficult part of LLVM to understand.
> The definition of MyRegisterClass is not so bad though, and perhaps it
> doesn't matter how it works under the hood to the average backend
> writer.
I agree with the complexity, but I would hope that more documentation,
examples and explanations would clarify it.
> What if RegisterClass contained a `list<RCInfo&...
2016 Sep 20
7
RFC: Implement variable-sized register classes
...pes; // The names of these members
IntSelect VarRegSize; // could likely be improved...
IntSelect VarSpillSize; //
IntSelect VarSpillAlignment //
}
To fully implement the AddReg instruction, the target would then define
the register class:
class MyRegisterClass : RegisterClass<...> {
let VarRegTypes = ValueTypeListSelect<[Mode64, Mode128],
[[i64, v2i32, v4i16, v8i8], // Mode64
[i128, v2i64, v4i32, v8i16, v16i8]]>; // Mode128
let VarRegSize = IntSelect<[Mode64, Mode128], [64, 128]>;
l...