Displaying 2 results from an estimated 2 matches for "myreg1_name".
2014 Jun 10
2
[LLVMdev] Regarding Instruction definition in LLVM backend
Hi all,
My question is related to the register usage in instruction definition at
TARGETInstrInfo.td file.
I have defined new Target with it Registers and instructions.
Now I need to generate an instruction like:
mov MYREG1_NAME, MYREG2_NAME
for the built-in function taking one constant integer argument, such as
"__builtin_my_function_name(88)"
I wondering whether it is possible to do this using only TableGen ?
I assume that I should only define a class in TARGETInstrInfo.td file.
Currently I have done the fo...
2014 Jun 10
2
[LLVMdev] Regarding Instruction definition in LLVM backend
Hi Tim,
Thank you for your response.
I need that immediate value latter to concatenate to registers' names (which
I am doing during assembly printing).
Also just Updating some status for my questioin:
I have continued with using *Defs* list. It allows me to keep Registers as
an implicit operands of /*MachineInstr*/ and later during its lowering pass
them to the /*MCInstr*/. Now seems I need