Displaying 3 results from an estimated 3 matches for "myreadvector".
2018 Nov 19
2
Per-write cycle count with ReadAdvance - Do I really need that?
It does not work. I have tried to use the latest master today. But tblgen
still give me information like
error: Resources are defined for both SchedRead and its alias on processor
MyArchModel
def : ReadAdvance<MyReadVector, 3, [MyWriteAddVector]>;
^
Unless I change "MyReadVector" to another read like "MyReadVector1", it
would not work. Debugging into tblgen, there is no path to handle multiplle
latencies for same Read...
Anyway as you reminded, I am searching for more Target and am looking in...
2018 Nov 17
2
Per-write cycle count with ReadAdvance - Do I really need that?
...MyWriteAddVector : SchedWriteRes<[MyArchVALU]> { let Latency = 6; }
> def MyWriteMulVector : SchedWriteRes<[MyArchVALU]> { let Latency = 6; }
> ...
>
> Here I defined 3 different Writes with same latency number. Below shows
> the forwarding.
>
> def : ReadAdvance<MyReadVector, 5, [WriteVector]>;
> def : ReadAdvance<MyReadVector, 3, [MyWriteAddVector_3cycles]>;
> def : ReadAdvance<MyReadVector, 1, [MyWriteMulVector_5cycles]>;
> ...
> def : ReadAdvance<MyReadStoreVector, 0, [WriteVector]>;
> def : ReadAdvance<MyReadStoreVector, 0, [M...
2018 Nov 15
2
Per-write cycle count with ReadAdvance - Do I really need that?
...t; { let Latency = 6; }
...
def MyWriteAddVector : SchedWriteRes<[MyArchVALU]> { let Latency = 6; }
def MyWriteMulVector : SchedWriteRes<[MyArchVALU]> { let Latency = 6; }
...
Here I defined 3 different Writes with same latency number. Below shows the
forwarding.
def : ReadAdvance<MyReadVector, 5, [WriteVector]>;
def : ReadAdvance<MyReadVector, 3, [MyWriteAddVector_3cycles]>;
def : ReadAdvance<MyReadVector, 1, [MyWriteMulVector_5cycles]>;
...
def : ReadAdvance<MyReadStoreVector, 0, [WriteVector]>;
def : ReadAdvance<MyReadStoreVector, 0, [MyWriteAddVector_3cycles]&...