search for: mypseudoinst

...so at instructions selection the original call %_tmp3 = call %rec6 @llvm.phx.divm.u16.rec6(i16 %_tmp1, i16 %_tmp2) has been lowered to t6: i16,i16 = llvm.phx.divm.u16 TargetConstant:i16<3778>, t2, t4 and the instruction I want to select also returns two values def divm16_pseudo : MyPseudoInst< (outs aNh_0_7:$dst, aNh_0_7:$dst2), (ins aNh_0_7:$src1, aNh_0_7:$src2)>; Both outs are i16. /Mikael

...target I have an intrinsic def int_phx_divm_u16 : Intrinsic<[llvm_any_ty], [llvm_i16_ty, llvm_i16_ty], [IntrNoMem]>; that I want to translate to the following instruction during instruction selection: def divm16_pseudo : MyPseudoInst< (outs aNh_0_7:$dst, aNh_0_7:$dst2), (ins aNh_0_7:$src1, aNh_0_7:$src2)>; So I've done a pattern the same way I've done for numerous other intrinsics (that returns simple types like i16/i32 etc): def : Pat<(int_phx_divm_u16 i16:$src1, i16:$src2), (divm16_pse...

...ll > > %_tmp3 = call %rec6 @llvm.phx.divm.u16.rec6(i16 %_tmp1, i16 %_tmp2) > > has been lowered to > > t6: i16,i16 = llvm.phx.divm.u16 TargetConstant:i16<3778>, t2, t4 > > and the instruction I want to select also returns two values > > def divm16_pseudo : MyPseudoInst< > (outs aNh_0_7:$dst, aNh_0_7:$dst2), > (ins aNh_0_7:$src1, aNh_0_7:$src2)>; > > Both outs are i16. > > /Mikael > The intrinsic itself should define multiple IR outputs rather than using any ty. I’m also not sure if tablegen currently supports patterns with mul...

...: Intrinsic<[llvm_any_ty], >> [llvm_i16_ty, llvm_i16_ty], >> [IntrNoMem]>; >> >> that I want to translate to the following instruction during instruction selection: >> >> def divm16_pseudo : MyPseudoInst< >> (outs aNh_0_7:$dst, aNh_0_7:$dst2), >> (ins aNh_0_7:$src1, aNh_0_7:$src2)>; >> >> So I've done a pattern the same way I've done for numerous other intrinsics (that returns simple types like i16/i32 etc): >> >> def : Pat<(int_phx_divm_...

...gt; def int_phx_divm_u16 : Intrinsic<[llvm_any_ty], > [llvm_i16_ty, llvm_i16_ty], > [IntrNoMem]>; > > that I want to translate to the following instruction during instruction selection: > > def divm16_pseudo : MyPseudoInst< > (outs aNh_0_7:$dst, aNh_0_7:$dst2), > (ins aNh_0_7:$src1, aNh_0_7:$src2)>; > > So I've done a pattern the same way I've done for numerous other intrinsics (that returns simple types like i16/i32 etc): > > def : Pat<(int_phx_divm_u16 i16:$src1, i16:$src2...

...%rec6 @llvm.phx.divm.u16.rec6(i16 %_tmp1, i16 %_tmp2) >> >> has been lowered to >> >> t6: i16,i16 = llvm.phx.divm.u16 TargetConstant:i16<3778>, t2, t4 >> >> and the instruction I want to select also returns two values >> >> def divm16_pseudo : MyPseudoInst< >> (outs aNh_0_7:$dst, aNh_0_7:$dst2), >> (ins aNh_0_7:$src1, aNh_0_7:$src2)>; >> >> Both outs are i16. >> >> /Mikael >> > > The intrinsic itself should define multiple IR outputs rather than using any ty. But the intrinsic returns a r...

> On Mar 30, 2016, at 11:35, Mikael Holmén <mikael.holmen at ericsson.com> wrote: > > i16 (divm16_pseudo …) > > stuff? > > I've tried > (i16, i16 (divm16_pseudo i16:$src1, i16:$src2) > and > ((i16, i16) (divm16_pseudo i16:$src1, i16:$src2) > and a few other variants without managing to get it through. > > Thanks again, > Mikael Are you

..._tmp1, i16 %_tmp2) >>> >>> has been lowered to >>> >>> t6: i16,i16 = llvm.phx.divm.u16 TargetConstant:i16<3778>, t2, t4 >>> >>> and the instruction I want to select also returns two values >>> >>> def divm16_pseudo : MyPseudoInst< >>> (outs aNh_0_7:$dst, aNh_0_7:$dst2), >>> (ins aNh_0_7:$src1, aNh_0_7:$src2)>; >>> >>> Both outs are i16. >>> >>> /Mikael >>> >> >> The intrinsic itself should define multiple IR outputs rather than using...

....i32.i32(i32, i32)* ******************************************************************************************* In InstroInfo.td, I define a pseudo instruction like this : ****************************************************************************************** *let isPseudo = 1 in {* * def FOO : MyPseudoInst<(outs GRRegs:$dst) , (ins GRRegs:$src1, GRRegs:$src2),* * "foo $dst, $src1, $src2",* * [(set i32:$dst, (int_foo i32:$src1, i32:$src2))]> {* * }* *} * ******************************************************************************************...

Hi, All, I want to add one intrinsic function for my particular backend. Let's say the intrinsic function is named "foo" which takes two i32 inputs and has one i32 output. First, I add this line "def int_foo : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrReadArgMem]>;" in /include/llvm/IR/Intrinsics.td. Then, in my target/InstrInfo.td, I'm supposed