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myip
2009 Jul 10
2
[LLVMdev] Help: Instruction Pattern Matching question
...i want to mix register types when I define the instruction for add,sub etc
I define the instruction TargetInstruction.td as follows:
class MyInst
<opcode op,subopcode subop,
dag outs, dag ins, string asmstr,list<dag> pattern>
Instruction
{
let Namespce = "MyNameSpace";
MyOpCode myop = op;
MySubOpcode mysubop = subop;
dag OutOprandList = outs;
dag InOprandList = ins;
let ASMString = asmstr;
let Pattern = pattern;
}
def My_ADDINST1: MyInst <MYADD1, NO_SUBOP,
(outs ptr_rc: $dest), (ins: $ptr_rc:$ptr1, Int32RC:$src)
"myadd1 $dst, $p...