Displaying 8 results from an estimated 8 matches for "myisd".
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2017 Sep 15
2
Changes to 'ADJCALLSTACK*' and 'callseq_*' between LLVM v4.0 and v5.0
...0x15c9bbd98, TargetConstant:i32<0>, TargetGlobalAddress:i32<void
(i8*, i32, i8*, i8*)* @__assert_func> 0, 0x15c9bbd98:1
0x15c9bb920: i32 = TargetConstant<0>
0x15c9bb8b8: i32 = TargetGlobalAddress<void (i8*, i32, i8*, i8*)*
@__assert_func> 0
0x15c9bbd98: ch,glue = MYISD::CALL 0x15c9bbcc8,
TargetGlobalAddress:i32<void (i8*, i32, i8*, i8*)* @__assert_func> 0,
Register:i32 %I18, Register:i32 %I17, Register:i32 %I16, Register:i32 %I15,
RegisterMask:Untyped, 0x15c9bbcc8:1
0x15c9bb8b8: i32 = TargetGlobalAddress<void (i8*, i32, i8*, i8*)*
@__assert_func>...
2017 Sep 15
0
Changes to 'ADJCALLSTACK*' and 'callseq_*' between LLVM v4.0 and v5.0
...2<0>,
> TargetGlobalAddress:i32<void
> (i8*, i32, i8*, i8*)* @__assert_func> 0, 0x15c9bbd98:1
> 0x15c9bb920: i32 = TargetConstant<0>
> 0x15c9bb8b8: i32 = TargetGlobalAddress<void (i8*, i32, i8*, i8*)*
> @__assert_func> 0
> 0x15c9bbd98: ch,glue = MYISD::CALL 0x15c9bbcc8,
> TargetGlobalAddress:i32<void (i8*, i32, i8*, i8*)* @__assert_func> 0,
> Register:i32 %I18, Register:i32 %I17, Register:i32 %I16, Register:i32 %I15,
> RegisterMask:Untyped, 0x15c9bbcc8:1
> 0x15c9bb8b8: i32 = TargetGlobalAddress<void (i8*, i32, i8*, i8*...
2017 Sep 19
1
Changes to 'ADJCALLSTACK*' and 'callseq_*' between LLVM v4.0 and v5.0
...[SDNPHasChain, SDNPOutGlue]>;
def MyCallseqEnd : SDNode<"ISD::CALLSEQ_END",
SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>,
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
def my_call : SDNode<"MyISD::CALL",
SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
def my_ret : SDNode<"MyISD::RET_FLAG",
SDTNone,
[SDNPHasChain, SDNPOptInGlue,...
2013 Apr 12
1
[LLVMdev] Problem with Store of i8 in a global address
...n InstrInfo.td:
def SDTmyCONST32 : SDTypeProfile<1, 1, [
SDTCisVT<0, i32>,
SDTCisVT<1, i32>,
SDTCisPtrTy<0>]>;
def myCONST32 : SDNode<"myISD::CONST32", SDTmyCONST32>;
def myCONST32_GP : SDNode<"myISD::CONST32_GP", SDTmyCONST32>;
let PrintMethod = "printDMemOperand" in
def globaladdress : Operand<i32>;
def STdb : STInst<(outs),
(ins globaladdress:$addr,...
2008 Dec 05
2
[LLVMdev] (tablegen) Machine instruction without result
...//2 inputs which are of the same type (int)
def NOResSDTIntBinOp : SDTypeProfile<0, 2, [
SDTCisSameAs<0, 1>, SDTCisInt<0>
]>;
//define a node using that profile with a OutFlag
//property (which is a way to modelise e.g. HW internal CC registers?)
def MYcmpicc : SDNode<"MYISD::CMPICC", NOResSDTIntBinOp, [SDNPOutFlag]>;
//define the instruction
def MYcmp : InstMYArch<(outs), (ins IntRegs:$src1, IntRegs:$src2),
"cmp $src1 $src2;",
[(MYcmpicc IntRegs:$src1, IntRegs:$src2)]>;
Thanks for having a...
2008 Dec 05
0
[LLVMdev] (tablegen) Machine instruction without result
...type (int)
> def NOResSDTIntBinOp : SDTypeProfile<0, 2, [
> SDTCisSameAs<0, 1>, SDTCisInt<0>
> ]>;
>
> //define a node using that profile with a OutFlag
> //property (which is a way to modelise e.g. HW internal CC registers?)
> def MYcmpicc : SDNode<"MYISD::CMPICC", NOResSDTIntBinOp,
> [SDNPOutFlag]>;
>
>
> //define the instruction
> def MYcmp : InstMYArch<(outs), (ins IntRegs:$src1, IntRegs:$src2),
> "cmp $src1 $src2;",
> [(MYcmpicc IntRegs:$src1, IntRegs:$...
2010 Jan 19
0
[LLVMdev] Frame index arithmetic
Hi Mark,
>> Sounds like your load / store address selection routine isn't working
>> like what you expected.
>>
>
> Thanks for the reply. Unfortunately, this doesn't seem to be the problem.
do you handle truncating stores and extending loads?
Ciao,
Duncan.
2010 Jan 19
2
[LLVMdev] Frame index arithmetic
>> I'm trying something cunning/crazy with the stack - implementing it in a type of memory that can only be addressed via immediates.
>>
>> I've got this mostly working. However, I came across a problem which I've been unable to work around: lowering the IR (even without any optimisations enabled) often requires the pattern:
>>
>> i32 = FrameIndex