Displaying 1 result from an estimated 1 matches for "myintreg".
2016 Sep 20
7
RFC: Implement variable-sized register classes
...e64
[i128, v2i64, v4i32, v8i16, v16i8]]>; // Mode128
let VarRegSize = IntSelect<[Mode64, Mode128], [64, 128]>;
let VarSpillSize = IntSelect<[Mode64, Mode128], [64, 128]>;
let VarSpillAlignment = IntSelect<[Mode64, Mode128], [64, 128]>;
}
def MyIntReg: MyRegisterClass { ... };
And following that, the instruction:
def AddReg: Instruction {
let OutOperandList = (outs MyIntReg:$Rd);
let InOperandList = (ins MyIntReg:$Rs, MyIntReg:$Rt);
let AsmString = "add $Rd, $Rs, $Rt";
let Pattern = [(set MyIntReg:$Rd, (add MyI...