Displaying 8 results from an estimated 8 matches for "myinstruction".
2013 Feb 08
0
[LLVMdev] llvm metadata transformation pass
...me structures (instructions/variables) and the
second pass is an analyzing pass which needs to access the added metadata.
The problem is with my adding metadata transformation pass. There might be
two problems(or both):
First, maybe I don't add correctly metadata.
LLVMContext& C = myInstruction->getContext();
MDNode* N = MDNode::get(C, MDString::get(C, "add info"));
myInstruction->setMetadata("important", N);
errs()<<"\n"<<cast<MDString>(myInstruction->getMetadata("important")->getOperand(0))->getSt...
2013 May 10
4
[LLVMdev] Predicated Vector Operations
...ink I get it now. This was mentioned earlier in the thread,
> but it didn't click at the time. It sounds like I can do instruction
> selection with a pattern like (omitting selection of the sources):
>
> let Constraints = "$dst = $oldvalue" in {
> def MASKEDARITH : MyInstruction<
> (outs VectorReg:$dst),
> (ins MaskReg:$mask, VectorReg:$src1, VectorReg:$src2,
> VectorReg:$oldvalue),
> "add $dst {$mask}, $src1, $src2",
> [(set v16i32:$dst, (vselect v16i1:$mask, (add v16i32:$src1,
> v16i32:$src2), v16i32:$oldvalu...
2013 Jan 31
2
[LLVMdev] Tablegen problem populating TSFlags
...= "Test"; }
def RC1 : RegisterClass<"Test", [i8], 8, (add r1)>;
class BitField<bits<2> x> {
bits<2> Val = x;
}
def VALUE_0 : BitField<0>;
def VALUE_1 : BitField<1>;
def VALUE_2 : BitField<2>;
def VALUE_3 : BitField<3>;
class MyInstruction<dag outs, dag ins, string asmstr, list<dag>
pattern> : Instruction
{
let Namespace = "Test";
let OutOperandList = outs;
let InOperandList = ins;
let AsmString = asmstr;
let Pattern = pattern;
bit Choice = 1;
BitField foo...
2013 May 11
0
[LLVMdev] Predicated Vector Operations
...his was mentioned earlier in the thread,
>> but it didn't click at the time. It sounds like I can do instruction
>> selection with a pattern like (omitting selection of the sources):
>>
>> let Constraints = "$dst = $oldvalue" in {
>> def MASKEDARITH : MyInstruction<
>> (outs VectorReg:$dst),
>> (ins MaskReg:$mask, VectorReg:$src1, VectorReg:$src2,
>> VectorReg:$oldvalue),
>> "add $dst {$mask}, $src1, $src2",
>> [(set v16i32:$dst, (vselect v16i1:$mask, (add v16i32:$src1,
>> v16i32...
2013 May 10
0
[LLVMdev] Predicated Vector Operations
Ah, I think I get it now. This was mentioned earlier in the thread,
but it didn't click at the time. It sounds like I can do instruction
selection with a pattern like (omitting selection of the sources):
let Constraints = "$dst = $oldvalue" in {
def MASKEDARITH : MyInstruction<
(outs VectorReg:$dst),
(ins MaskReg:$mask, VectorReg:$src1, VectorReg:$src2,
VectorReg:$oldvalue),
"add $dst {$mask}, $src1, $src2",
[(set v16i32:$dst, (vselect v16i1:$mask, (add v16i32:$src1,
v16i32:$src2), v16i32:$oldvalue))]>;
}
That's actual...
2013 May 09
2
[LLVMdev] Predicated Vector Operations
On May 9, 2013, at 3:05 PM, Jeff Bush <jeffbush001 at gmail.com> wrote:
> On Thu, May 9, 2013 at 8:10 AM, <dag at cray.com> wrote:
>> Jeff Bush <jeffbush001 at gmail.com> writes:
>>
>>> %tx = select %mask, %x, <0.0, 0.0, 0.0 ...>
>>> %ty = select %mask, %y, <0.0, 0.0, 0.0 ...>
>>> %sum = fadd %tx, %ty
>>> %newvalue
2011 Jun 24
1
[LLVMdev] unmodeled side effects
Hi
A bunch of instructions that I have defined in tablegen files get
tagged with unmodeledSideEffect property. I have defined these
instructions with no corresponding dag patterns. Is there a way i can
avoid this property and say they do not have any side effects
thanks
shrey
2013 May 10
0
[LLVMdev] Predicated Vector Operations
...his was mentioned earlier in the thread,
>> but it didn't click at the time. It sounds like I can do instruction
>> selection with a pattern like (omitting selection of the sources):
>>
>> let Constraints = "$dst = $oldvalue" in {
>> def MASKEDARITH : MyInstruction<
>> (outs VectorReg:$dst),
>> (ins MaskReg:$mask, VectorReg:$src1, VectorReg:$src2,
>> VectorReg:$oldvalue),
>> "add $dst {$mask}, $src1, $src2",
>> [(set v16i32:$dst, (vselect v16i1:$mask, (add v16i32:$src1,
>> v16i32:$sr...