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2013 Jan 31
2
[LLVMdev] Tablegen problem populating TSFlags
It seems like this code should work with Tablegen, but it generates the error: "error:Invalid TSFlags bit in ADD" Here's the code: =================================== include "llvm/Target/Target.td" def MyInstrInfo : InstrInfo; def MyTarget : Target { // Information about the instructions... let InstructionSet = MyInstrInfo; } def r1 : Register<"r1"> { let Namespace = "Test"; } def RC1 : RegisterClass<"Test", [i8], 8, (add r1)>; class BitField<bits<2>...