Displaying 5 results from an estimated 5 matches for "my_fmdrr".
2009 Feb 19
1
[LLVMdev] help: about how to use tblgen to constraint operand.
...define a pattern to move two 32bits gpr to 64bits fpr. like arm instructure fmdrr.
But I need to use an even/odd register pair to save its 2 operands.
I define in mytarget.td:
myfmdrr:
SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
SDTCisSameAs<1, 2>]>;
def my_fmdrr : ...........
def myFMDRR : ....
(outs FPR: $result), ins(GPR: $op1, GPR:$op2 )
[(setFPR: $result, (my_fmdrr GPR: $op1, GPR:$op2) )]
I create myfmdrr instructure in mytargetISelLowering.cpp. and its operands are in R0 and R1.
But after optimization, the...
2009 Feb 20
2
[LLVMdev] help: about how to use tblgen to constraint operand.
...efine a pattern to move two 32bits gpr to 64bits fpr. like arm instructure fmdrr.
But I need to use an even/odd register pair to save its 2 operands.
I define in mytarget.td:
myfmdrr:
SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
SDTCisSameAs<1, 2>]>;
def my_fmdrr : ...........
def myFMDRR : ....
(outs FPR: $result), ins(GPR: $op1, GPR:$op2 )
[(setFPR: $result, (my_fmdrr GPR: $op1, GPR:$op2) )]
I create myfmdrr instructure in mytargetISelLowering.cpp. and its operands are in R0 and R1.
But after optimization, the...
2009 Feb 20
0
[LLVMdev] help: about how to use tblgen to constraint operand.
...> instructure fmdrr.
>> But I need to use an even/odd register pair to save its 2 operands.
>> I define in mytarget.td:
>>
>> myfmdrr:
>> SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
>> SDTCisSameAs<1, 2>]>;
>> def my_fmdrr : ...........
>> def myFMDRR : ....
>> (outs FPR: $result), ins(GPR: $op1, GPR:$op2 )
>> [(setFPR: $result, (my_fmdrr GPR: $op1, GPR:
>> $op2) )]
>>
>> I create myfmdrr instructure in mytargetISelLowering.cpp. and its...
2009 Mar 30
1
[LLVMdev] Dear Evan Chang, Re: help: about how to use tblgen to constraint operand.
...efine a pattern to move two 32bits gpr to 64bits fpr. like arm instructure fmdrr.
But I need to use an even/odd register pair to save its 2 operands.
I define in mytarget.td:
myfmdrr:
SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
SDTCisSameAs<1, 2>]>;
def my_fmdrr : ...........
def myFMDRR : ....
(outs FPR: $result), ins(GPR: $op1, GPR:$op2 )
[(setFPR: $result, (my_fmdrr GPR: $op1, GPR:$op2) )]
I create myfmdrr instructure in mytargetISelLowering.cpp. and its operands are in R0 and R1.
But after optimization, the...
2009 Mar 31
1
[LLVMdev] 转发: Re: Dear Evan Chang, Re: help: about how to use tblgen to constraint operand.
...fine a pattern to move two 32bits gpr to 64bits fpr. like arm instructure fmdrr.
But I need to use an even/odd register pair to save its 2 operands.
I define in mytarget.td:
myfmdrr:
SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
SDTCisSameAs<1, 2>]>;
def my_fmdrr : ...........
def myFMDRR : ....
(outs FPR: $result), ins(GPR: $op1, GPR:$op2 )
[(setFPR: $result, (my_fmdrr GPR: $op1, GPR:$op2) )]
I create myfmdrr instructure in mytargetISelLowering.cpp. and its operands are in R0 and R1.
But after optimization, the...