search for: mwait_idle_with_hints

I am trying to experiment with lhype on a 32bit Intel box and when I launch a guest I get the following oops message: ----------- invalid opcode: 0000 [#1] Modules linked in: CPU: 0 EIP: 0061:[<c0101223>] Not tainted VLI EFLAGS: 00010246 (2.6.20-rc2 #1) EIP is at mwait_idle_with_hints+0x1e/0x3a eax: c03c8008 ebx: 00000000 ecx: 00000000 edx: 00000000 esi: 00000000 edi: c03c8008 ebp: 4c687970 esp: c03c9f74 ds: 007b es: 007b ss: 0069 Process swapper (pid: 0, ti=c03c8000 task=c039c420 task.ti=c03c8000) Stack: 00000000 c040102c c03fd120 c0101333 c03ca693 c0344d03 c03c...

I am trying to experiment with lhype on a 32bit Intel box and when I launch a guest I get the following oops message: ----------- invalid opcode: 0000 [#1] Modules linked in: CPU: 0 EIP: 0061:[<c0101223>] Not tainted VLI EFLAGS: 00010246 (2.6.20-rc2 #1) EIP is at mwait_idle_with_hints+0x1e/0x3a eax: c03c8008 ebx: 00000000 ecx: 00000000 edx: 00000000 esi: 00000000 edi: c03c8008 ebp: 4c687970 esp: c03c9f74 ds: 007b es: 007b ss: 0069 Process swapper (pid: 0, ti=c03c8000 task=c039c420 task.ti=c03c8000) Stack: 00000000 c040102c c03fd120 c0101333 c03ca693 c0344d03 c03c...

...>] run_timer_softirq+0x163/0x189 [<f8b8b40a>] htb_rate_timer+0x0/0xc4 [sch_htb] [<c0123315>] __do_softirq+0x70/0xdb [<c01233bb>] do_softirq+0x3b/0x42 [<c0111cda>] smp_apic_timer_interrupt+0x9c/0xb2 [<c0104373>] apic_timer_interrupt+0x1f/0x24 [<c0101cc3>] mwait_idle_with_hints+0x3b/0x3f [<c0101cd3>] mwait_idle+0xc/0x1b [<c010271c>] cpu_idle+0x63/0x79 ======================= BUG: soft lockup detected on CPU#2! [<c013c890>] softlockup_tick+0x93/0xc2 [<c0127585>] update_process_times+0x26/0x5c [<c0111cd5>] smp_apic_timer_interrupt+0x97/0x...

.../arch/x86/acpi/cpu_idle.c Fri Feb 18 19:07:11 2011 +0000 +++ b/xen/arch/x86/acpi/cpu_idle.c Wed Feb 23 17:05:32 2011 +0800 @@ -569,7 +569,8 @@ static void acpi_dead_idle(void) { case ACPI_CSTATE_EM_FFH: /* Not treat interrupt as break event */ - mwait_idle_with_hints(cx->address, 0); + __monitor((void *)&mwait_wakeup(smp_processor_id()), 0, 0); + __mwait(cx->address, 0); break; case ACPI_CSTATE_EM_SYSIO: inb(cx->address); _______________________________________________...

...t guaranteed to be ordered by any other fencing or serializing instructions or by another CLFLUSH instruction. For example, software can use an MFENCE instruction to ensure that previous stores are included in the write-back. There are instances of this in mwait_play_dead, clflush_cache_range, mwait_idle_with_hints, mwait_idle .. A comment near pcommit_sfence includes an example flush_and_commit_buffer code which is interesting - it assumes sfence flushes clflush. So it appears that pcommit_sfence in that file is wrong then? At least on processors where it falls back on clflush. mwait_idle is the only one...

...t guaranteed to be ordered by any other fencing or serializing instructions or by another CLFLUSH instruction. For example, software can use an MFENCE instruction to ensure that previous stores are included in the write-back. There are instances of this in mwait_play_dead, clflush_cache_range, mwait_idle_with_hints, mwait_idle .. A comment near pcommit_sfence includes an example flush_and_commit_buffer code which is interesting - it assumes sfence flushes clflush. So it appears that pcommit_sfence in that file is wrong then? At least on processors where it falls back on clflush. mwait_idle is the only one...

What is the point of specifying "current" as the address to monitor? The memory location of interest really is irq_stat[cpu].__softirq_pending, and if that was used it would then also be possible to actually avoid sending IPIs when monitor/mwait are in use, as is being done on Linux. Jan _______________________________________________ Xen-devel mailing list

On Tue, Jan 12, 2016 at 02:25:24PM -0800, H. Peter Anvin wrote: > On 01/12/16 14:10, Michael S. Tsirkin wrote: > > mb() typically uses mfence on modern x86, but a micro-benchmark shows that it's > > 2 to 3 times slower than lock; addl $0,(%%e/rsp) that we use on older CPUs. > > > > So let's use the locked variant everywhere - helps keep the code simple as >

On Tue, Jan 12, 2016 at 02:25:24PM -0800, H. Peter Anvin wrote: > On 01/12/16 14:10, Michael S. Tsirkin wrote: > > mb() typically uses mfence on modern x86, but a micro-benchmark shows that it's > > 2 to 3 times slower than lock; addl $0,(%%e/rsp) that we use on older CPUs. > > > > So let's use the locked variant everywhere - helps keep the code simple as >

...lt;c04541e6>] handle_IRQ_event+0x1a/0x3f [<c04553f5>] handle_fasteoi_irq+0x64/0x98 [<c0455391>] handle_fasteoi_irq+0x0/0x98 [<c04071f7>] do_IRQ+0xac/0xd1 [<c041ad1f>] smp_apic_timer_interrupt+0x74/0x80 [<c040592b>] common_interrupt+0x23/0x28 [<c0403281>] mwait_idle_with_hints+0x3b/0x3f [<c0403285>] mwait_idle+0x0/0xa [<c04033c9>] cpu_idle+0x96/0xb7 [<c0764a8e>] start_kernel+0x316/0x31e [<c0764227>] unknown_bootoption+0x0/0x202 ======================= Code: 40 54 00 00 00 00 c7 40 58 00 00 00 00 eb 14 89 50 44 c7 40 50 00 00 00 00 89 48 54 8b...

Patch 1 removes CONFIG_SMP Patch 2 removes separate smp_{,r,w}mb()s as a result of patch 1 Patch 4 removes __ia64__ defines from the x86 arch tree Patch 3 is related to patch 4 and changes the VIOAPIC to emulate version 0x20 as a performance gain. It preceeds Patch 4 so as to be more clear about the functional change. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>

...ware name: LG Electronics R510/QL8, BIOS QL8L3B42 07/30/2008 Dec 21 00:44:20 ycradnileved kernel: [ 3839.488055] task: ffff8800beeea780 ti: ffff8800bef0a000 task.ti: ffff8800bef0a000 Dec 21 00:44:20 ycradnileved kernel: [ 3839.488055] RIP: 0010:[<ffffffff8103a56e>] [<ffffffff8103a56e>] mwait_idle_with_hints+0x5e/0x70 Dec 21 00:44:20 ycradnileved kernel: [ 3839.488055] RSP: 0018:ffff8800bef0be30 EFLAGS: 00000046 Dec 21 00:44:20 ycradnileved kernel: [ 3839.488055] RAX: 0000000000000020 RBX: ffff8800bee7cc00 RCX: 0000000000000001 Dec 21 00:44:20 ycradnileved kernel: [ 3839.488055] RDX: 0000000000000000...