Displaying 3 results from an estimated 3 matches for "mvnlt".
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mvnet
2010 Nov 12
0
[LLVMdev] Simplifying selects + arm stuff
...-o - -march=arm
> _test: @ @test
> @ BB#0:
> cmp r0, r1
> mvn r12, #0
> movlt r2, r12
> and r0, r2, r3
> bx lr
>
> is better than a cmp + conditional and + bx.
This should be
cmp r0, r1
movlt.w r2, #-1 @ or mvnlt r2, #0
and.w r0, r2, r3
bx lr
which we gets right in Thumb2 mode (I need to check why it's not matching in ARM mode). How can we use a conditional and here? The result is either (y & -1) or (y & x), the "and" is not conditional.
Evan
>
> -Chris...
2010 Nov 12
1
[LLVMdev] Simplifying selects + arm stuff
On Nov 12, 2010, at 11:46 AM, Evan Cheng wrote:
>
> This should be
>
> cmp r0, r1
> movlt.w r2, #-1 @ or mvnlt r2, #0
> and.w r0, r2, r3
> bx lr
>
> which we gets right in Thumb2 mode (I need to check why it's not matching in ARM mode). How can we use a conditional and here? The result is either (y & -1) or (y & x), the "and" is not conditional.
y&...
2010 Nov 12
2
[LLVMdev] Simplifying selects + arm stuff
On Nov 12, 2010, at 11:04 AM, Evan Cheng wrote:
>> %z = select i1 %cond, i32 -1, i32 %x
>> %s = and i32 %z, %y
>>
>> Is a "conditional and". It would be interesting to know if the ARM backend gets this as a single predicated 'and' instruction (similarly for the 'or' and 'xor' version of these patterns). I bet not, which is bad if