search for: mv_any16

...N40_0_7:%vreg1954 [5000r,5056r:0)[5056r,5348r:1) 0 at 5000r 1 at 5056r At this point I have the following live ranges for vreg1954: %vreg1954 [5000r,5056r:0)[5056r,5348r:1) 0 at 5000r 1 at 5056r And vreg1954 is mentioned in these instructions: 5000B %vreg1954:hi16<def,read-undef> = mv_any16 32766 [...] 5048B mv_ar16_r16_rmod1 %vreg1954:hi16, %vreg1753 5056B %vreg1954:lo16<def> = mv_nimm6_ar16 0 5064B Store40FI %vreg1954, <fi#2> [...] 5128B %vreg223<def> = COPY %vreg1954 [...] 5216B %vreg1178<def> = COPY %vreg1954 [...] 5348B %vreg1955&...

Hi, I'm having some trouble understanding if the live intervals calculated for one of my testcases are correct or not. I have the following instructions: 272L %vreg67:lo<def> = mv_any16 65535; R:%vreg67 288L %vreg64:hi<def> = mv_any16 16383; R:%vreg64 304L %vreg64:lo<def> = COPY %vreg67:lo; R:%vreg64,%vreg67 320L %vreg6<def> = COPY %vreg64<kill>; R:%vreg6,%vreg64 So, %vreg64, which has two (disjunct) sub registers, gets its two parts written at 288 and 3...

Hi Quentin, On 08/15/14 19:01, Quentin Colombet wrote: [...] >> The question is: How should true subregister definitions be >> expressed so that they do not interfere with each other? See the >> detailed problem description below. > > We do have a limitation in our current liveness tracking for > sub-register. Therefore, I am not sure that is possible. > >

...a register. # *** IR Dump Before Linear Scan Register Allocator ***: # Machine code for function accumconv: Function Live Ins: %a0_gh in %vreg0, %a1_gh in %vreg1 BB#0: derived from LLVM BB %0 Live Ins: %a0_gh %a1_gh %vreg1<def> = COPY %a1_gh; aNgh_0_7:%vreg1 [...] %vreg56<def> = mv_any16 0; aNl_0_7:%vreg56 %vreg57<def> = REG_SEQUENCE %vreg1, hi24, %vreg56, lo16; aN40_0_7:%vreg57 aNgh_0_7:%vreg1 aNl_0_7:%vreg56 So the in-argument in a1_gh is saved in vreg1, and used later in a REG_SEQUENCE instruction to write a full register, vreg57. After the REG_SEQUENCE has been elimina...

...nitions be expressed so that they do not interfere with each other? See the detailed problem description below. --- During RA it's decided Reg5 should be spilled and it's also decided Reg5 can be rematerialized: "Value Reg5:0 at 5000r may remat from Reg5:hi16<def,read-undef> = mv_any16 32766" So it says Reg5 can be rematerialized by setting it's high part... We also get: reload: 5052r Reg5<def> = Load40FI <fi#2> rewrite: 5056r Reg5:lo16<def> = mv_nimm6_ar16 0 So it inserts a reload of the full Reg5 prior to the setting of Reg5:lo...