Displaying 3 results from an estimated 3 matches for "mv_a32_r16_rmod1".
2016 Mar 04
2
PHI node to different register class vs TailDuplication
...lt;kill>; aNlh_rN:%vreg13 rN:%vreg12
brr_uncond <BB#4>;
Successors according to CFG: BB#4(?%)
BB#4: derived from LLVM BB %bb4
Predecessors according to CFG: BB#2 BB#3
%vreg2<def> = PHI %vreg0, <BB#2>, %vreg1, <BB#3>; rN:%vreg2
aNlh_0_7:%vreg0 aNlh_rN:%vreg1
mv_a32_r16_rmod1 %vreg3, %vreg2; aN32_0_7:%vreg3 rN:%vreg2
brr_uncond <BB#6>;
Successors according to CFG: BB#6(?%)
Then TailDuplication runs
Tail-duplicating into PredBB: BB#2: derived from LLVM BB %bb2
[...]
From Succ: BB#4: derived from LLVM BB %bb4
and we get:
BB#2: derived from LLVM BB %bb2...
2014 Aug 19
2
[LLVMdev] Help with definition of subregisters; spill, rematerialization and implicit uses
...ioPass.cpp, but then I run into stuff like this instead:
832B %vreg50:hi16<def,read-undef> = COPY %vreg0
848B ...
864B %vreg19<def,dead> = COPY %vreg50
880B %vreg19:lo16<def,read-undef> = COPY %vreg73
896B ...
912B mv_a32_r16_rmod1 %vreg19, %vreg20
...
*** Bad machine code: Multiple connected components in live interval ***
- function: fixedconv
- interval: %vreg19 [864r,864d:0)[880r,1024r:1) 0 at 864r 1 at 880r
0: valnos 0
1: valnos 1
So here, both the setting of the hi16 and lo16 parts are marked with
read-undef,...
2014 Aug 15
2
[LLVMdev] Help with definition of subregisters; spill, rematerialization and implicit uses
Hi,
I have a problem regarding sub-register definitions and LiveIntervals on
our target. When a subregister is defined, other parts of the register
are always left untouched - they are neither read or def:ed.
It however seems that Codegen treats subregister definitions as somehow
clobbering the whole register.
The SSA-code looks like this after isel:
(Reg0 and Reg1 are 16bit registers. Reg2,