Displaying 2 results from an estimated 2 matches for "mulsu".
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muls
2017 Feb 26
2
When AVR backend generates mulsu instruction ?
Hello LLVMDevs,
I am looking for an example for how to lower LLVM IR to mulsu kind of
instruction. I found that AVR back end have such instruction but
AVRInstrInfo.td does not define any DAG pattern for which this
instruction gets emitted.
def MULSURdRr : FMUL2RdRr<1,
(outs),
(ins GPR8:$lhs, GPR8:$rhs),
"mulsu\t$lhs, $rhs",
[]>,
Requires<[SupportsMultipli...
2017 Feb 27
2
When AVR backend generates mulsu instruction ?
...r. I think I also need to write some code probably as
you indicated to check signedness of the operands and based on that lower
to mulhsu instruction.
-Vivek
On Mon, Feb 27, 2017 at 11:13 AM, Dylan McKay <me at dylanmckay.io> wrote:
> Hey Vivek,
>
> We don't directly emit the MULSURdRr instruction. On top of this, I don't
> believe any of the AVR multiplication instructions have patterns in
> TableGen.
>
> This is because the AVR mul instructions are quite strange. Almost all of
> the other instructions of the 'Rd, Rr' format take the values of Rd a...