Displaying 2 results from an estimated 2 matches for "mulssrr".
2011 Mar 19
1
[LLVMdev] X86 instruction encoding
Hi all,
Just a quick question about the X86 instruction naming convention in
LLVM. Most instruction names in LLVM are self-explanatory. Some are a
little confusing. What is the difference between instruction MULSSrr and
MULSSrr_Int? What does the suffix '_Int' stand for? Are these
instructions exchangeable: "ST_F64m", "ST_FP64m", "ST_Fp64m"
"ST_FpP64m32"? Any direction will be appreciated. Thanks a lot in advance.
Bin
2013 Dec 05
3
[LLVMdev] X86 - Help on fixing a poor code generation bug
...> = #OPCODE#SSrr X<kill,tied0>, Y
+ // Y<def,tied1> = #INSERT#SSrr Y<kill,tied0>, X<kill>
+ // ==>
+ // Y<def,tied1> = #OPCODE#SSrr Y<kill,tied0>, X<kill>
+ if (I->getOpcode() == X86::ADDSSrr ||
+ I->getOpcode() == X86::MULSSrr) {
+ unsigned Def = I->getOperand(2).getReg();
+
+ DenseMap<unsigned, MachineInstr*>::iterator CI = Candidates.find(Def);
+ if (CI != Candidates.end()) {
+ MachineOperand &MO = I->getOperand(0);
+ MachineInstr *CMI = CI->second;
+
+ if (...