Displaying 3 results from an estimated 3 matches for "mulsdrm".
2017 Feb 14
2
Adding FP environment register modeling for constrained FP nodes
...not always) comes from TargetInstrInfo queries based on the opcode. If this is right, then I’d need to introduce a new machine opcode for any instruction that I wanted to have an implicit register use. For instance, if we just mutated ISD::STRICT_FADD to ISD::FADD and Select changed that to X86::MULSDrm, then to attach implicit MXCSR use to that I’d need a new opcode (X86::MULSDrm_Strict) that behaves just like X86::MULSDrm but has the implicit MXCSR use/def information associated with it.
Does it sound like I’m understanding this correctly?
You're correct that implicit operands normally com...
2018 Feb 28
0
Missed optimization - spill/load generated instead of reg-to-reg move (and two other questions)
On 02/27/2018 10:21 AM, Alex Wang via llvm-dev wrote:
> Hello all!
>
> I was looking through the results of disassembling a heavily-used
> short function
> in the program I'm working on, and ended up wondering why LLVM was
> generating
> that assembly and what changes would be necessary to improve the code.
> I asked
> on #llvm, but it seems that the people with
2018 Feb 27
2
Missed optimization - spill/load generated instead of reg-to-reg move (and two other questions)
Hello all!
I was looking through the results of disassembling a heavily-used short function
in the program I'm working on, and ended up wondering why LLVM was generating
that assembly and what changes would be necessary to improve the code. I asked
on #llvm, but it seems that the people with the necessary expertise weren't
around.
Here is a condensed version of the code: