Displaying 5 results from an estimated 5 matches for "mulrdrr".
2010 Sep 09
2
[LLVMdev] Possible missed optimization? 2.0
...6:1)[54,62:2)[94,110:0) 0 at 94-(110) 1 at 38-(46) 2 at 54-(62)
R15,inf = [0,38:0)[110,118:2)[118,146:1) 0 at 0*-(38) 1 at 118-(146) 2 at 110-(118)
R13,inf = [0,94:0) 0 at 0*-(94)
%reg1029,0.000000e+00 = [62,134:0) 0 at 62-(134)
********** MACHINEINSTRS **********
BB#0: # derived from entry
36 MULRdRr %R12, %R15<kill>, %R1<imp-def,dead>, %R0<imp-def>
44 %reg1028<def> = MOVRdRr %R0<kill>
52 MULRdRr %R12<kill>, %R14, %R1<imp-def>, %R0<imp-def>
60 %reg1029<def> = MOVRdRr %R0<kill>
76 %reg1031<def> = MOVRdRr %R1<kill>
84 %reg103...
2017 Feb 27
2
When AVR backend generates mulsu instruction ?
...fit into TableGen and so we perform custom lowering
> for these nodes.
>
> We expand the MUL DAG node into 'ISD::UMUL_LOHI' or 'ISD::SMUL_LOHI'. We
> see these in AVRISelDAGToDAG.cpp and custom lower them (see
> AVRISelDAGToDAG::selectMultiplication) into MULSRdRr or MULRdRr,
> depending on signedness. Later on we have a custom inserter which inserts
> instructions to clear the r1,r0 scratch registers after use.
>
> The MULSURdRr instruction you mentioned is not generated by LLVM unless
> you use it yourself as part of some inline assembly.
>
> On...
2017 Feb 26
2
When AVR backend generates mulsu instruction ?
Hello LLVMDevs,
I am looking for an example for how to lower LLVM IR to mulsu kind of
instruction. I found that AVR back end have such instruction but
AVRInstrInfo.td does not define any DAG pattern for which this
instruction gets emitted.
def MULSURdRr : FMUL2RdRr<1,
(outs),
(ins GPR8:$lhs, GPR8:$rhs),
"mulsu\t$lhs, $rhs",
[]>,
Requires<[SupportsMultiplication]>;
Also
2010 Sep 09
2
[LLVMdev] Possible missed optimization? 2.0
...electionDAG code, i used X86's MUL code and adapted it to my
target:
case ISD::SMUL_LOHI:
case ISD::UMUL_LOHI:
{
SDValue Op1 = N->getOperand(0);
SDValue Op2 = N->getOperand(1);
unsigned LoReg = R0, HiReg = R1;
unsigned Opc = MULRdRr;
SDValue InFlag = SDValue(CurDAG->getMachineNode(Opc,
dl,
MVT::Flag,
Op1,...
2010 Sep 09
0
[LLVMdev] Possible missed optimization? 2.0
On Sep 9, 2010, at 12:59 PM, Borja Ferrer wrote:
> Hello, i've noticed a new possible missed optimization while testing more trivial code.
> This time it's not a with a xor but with a multiplication instruction and the example is little bit more involved.
>
> C code:
>
> typedef short t;
> t foo(t a, t b)
> {
> t a4 = a*b;
> return a4;
> }
>