Displaying 3 results from an estimated 3 matches for "mulhsu".
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2017 Feb 27
2
When AVR backend generates mulsu instruction ?
Thanks Dylan,
I am working on a backend which has mulhsu instruction that performs
multiplication between signed and unsigned number and returns upper 32 bits
into result register. I think I also need to write some code probably as
you indicated to check signedness of the operands and based on that lower
to mulhsu instruction.
-Vivek
On Mon, Feb 27, 2...
2020 Mar 27
3
llvm-objdump cannot recognize mul&mulh RISC-V M Instructions
...IR)/build/$@/$@.S
$(RISCV_LLVM_OBJDUMP) --arch=rv32imac -D $(WORK_DIR)/build/$@/$@ >
$(WORK_DIR)/build/$@/$@.ASM
```
gcc objdump result:
```
4001168: 00052383 lw t2,0(a0)
400116c: 979a add a5,a5,t1
400116e: 439c lw a5,0(a5)
4001170: 0308a533 mulhsu a0,a7,a6
```
llvm-objdump result:
```
4001168: 83 23 05 00 lw t2, 0(a0)
400116c: 9a 97 add a5, a5, t1
400116e: 9c 43 lw a5, 0(a5)
4001170: 33 a5 08 03 <unknown>
```
Does anyone knows what is the problem...
2017 Feb 26
2
When AVR backend generates mulsu instruction ?
Hello LLVMDevs,
I am looking for an example for how to lower LLVM IR to mulsu kind of
instruction. I found that AVR back end have such instruction but
AVRInstrInfo.td does not define any DAG pattern for which this
instruction gets emitted.
def MULSURdRr : FMUL2RdRr<1,
(outs),
(ins GPR8:$lhs, GPR8:$rhs),
"mulsu\t$lhs, $rhs",
[]>,
Requires<[SupportsMultiplication]>;
Also