Displaying 7 results from an estimated 7 matches for "mul_i64".
2013 Jul 30
3
[LLVMdev] Help with promotion/custom handling of MUL i32 and MUL i64
...i32 would generate a
64-bit results from the lower 32-bit portions of 64-bit source operands.
In customize for the operations, I am trying to do something like:
case ISD::MUL:
{
EVT OpVT = Op.getValueType();
if (OpVT == MVT::i64) {
RTLIB::Libcall LC = RTLIB::MUL_I64;
SDValue Dummy;
return ExpandLibCall(LC, Op, DAG, false, Dummy, *this);
}
else if (OpVT == MVT::i32){
??? What to do here to not have issues with type i32
}
}
I've gone a few directions on this.
Defining the architect...
2013 Jul 30
0
[LLVMdev] Help with promotion/custom handling of MUL i32 and MUL i64
...the lower 32-bit portions of 64-bit source operands.
>
> In customize for the operations, I am trying to do something like:
>
> case ISD::MUL:
> {
> EVT OpVT = Op.getValueType();
> if (OpVT == MVT::i64) {
> RTLIB::Libcall LC = RTLIB::MUL_I64;
> SDValue Dummy;
> return ExpandLibCall(LC, Op, DAG, false, Dummy, *this);
> }
> else if (OpVT == MVT::i32){
>
> ??? What to do here to not have issues with type i32
> }
> }
>
>
> I've...
2017 Oct 05
3
Bug 20871 -- is there a fix or work around?
Looks like I have run into the same issue reported in:
https://bugs.llvm.org/show_bug.cgi?id=20871
Is there a fix or work-around for it? The bug report seems to be still open.
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2013 Jul 31
2
[LLVMdev] Help with promotion/custom handling of MUL i32 and MUL i64
...ource operands.
> >
> > In customize for the operations, I am trying to do something like:
> >
> > case ISD::MUL:
> > {
> > EVT OpVT = Op.getValueType();
> > if (OpVT == MVT::i64) {
> > RTLIB::Libcall LC = RTLIB::MUL_I64;
> > SDValue Dummy;
> > return ExpandLibCall(LC, Op, DAG, false, Dummy, *this);
> > }
> > else if (OpVT == MVT::i32){
> >
> > ??? What to do here to not have issues with type i32
> > }
> &...
2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
> Can you explain why you chose the approach of using a new pass?
> I pictured removing LegalizeDAG's type legalization code would
> mostly consist of finding all the places that use TLI.getTypeAction
> and just deleting code for handling its Expand and Promote. Are you
> anticipating something more
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On May 20, 2009, at 1:34 PM, Eli Friedman wrote:
> On Wed, May 20, 2009 at 1:19 PM, Eli Friedman
> <eli.friedman at gmail.com> wrote:
>
>> Per subject, this patch adding an additional pass to handle vector
>>
>> operations; the idea is that this allows removing the code from
>>
>> LegalizeDAG that handles illegal types, which should be a significant
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...::MUL, dl, NVT, LL, RH);
- LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
- Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
- Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
- break;
- }
- }
-
- // If nothing else, we can make a libcall.
- Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
- break;
- }
- case ISD::SDIV:
- Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
- break;
- case ISD::UDIV:
- Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
- break;
- case ISD::SREM:
- Lo = ExpandLibCall(RTLIB::SREM_I64, Node,...