Displaying 3 results from an estimated 3 matches for "mul_1".
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2009 Feb 13
3
[LLVMdev] Modeling GPU vector registers, again (with my implementation)
...ions. When
the second write happens, I generate a shufflevector to multiplex the
existing value and the new value, and store the result of shufflevector.
Input assembly language:
mul r0.xy, r1, r2
add r0.zw, r3, r4
sub r5, r0, r1
is converted to LLVM IR:
%r0 = alloca <4 x float>
%mul_1 = mul <4 x float> %r1, %r2
store <4 x float> %mul_1, <4 x float>* %r0
...
%add_1 = add <4 x float> %r3, %r4
; a store does not immediately happen here
%load_1 = load <4 x float>* %r0
; select the first two elements from the existing value,
; the last two...
2009 Feb 13
0
[LLVMdev] Modeling GPU vector registers, again (with my implementation)
...ctor to multiplex the
> existing value and the new value, and store the result of
> shufflevector.
>
> Input assembly language:
> mul r0.xy, r1, r2
> add r0.zw, r3, r4
> sub r5, r0, r1
>
> is converted to LLVM IR:
>
> %r0 = alloca <4 x float>
> %mul_1 = mul <4 x float> %r1, %r2
> store <4 x float> %mul_1, <4 x float>* %r0
> ...
> %add_1 = add <4 x float> %r3, %r4
> ; a store does not immediately happen here
> %load_1 = load <4 x float>* %r0
>
> ; select the first two elements from th...
2009 Jan 14
2
[LLVMdev] Use two ComplexPatterns (possible bug of TableGen?)
...e or not).
In the following example, two 'regsw' are used to match the operands of mul.
def regsw : Operand<v4i32>,
ComplexPattern<v4i32, 2, "SelectRegsw", []> {
let PrintMethod = "printSrcReg";
let MIOperandInfo = (ops VR128, i8imm);
}
def MUL_1 : FooInst<(outs VR128:$dst),
(ins regsw:$src0, regsw:$src1),
"mul $dst, $src0, $src1",
[(set VR128:$dst, (mul regsw:$src0, regsw:$src1))]>;
The code generate by TableGen is:
SDNode *Select_ISD_MUL_v4i32(const SDValue &am...