Displaying 8 results from an estimated 8 matches for "mul32r".
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mul32
2013 Apr 25
2
[LLVMdev] [PATCH] Handle tied sub-operands in AsmMatcherEmitter
...gt; registers. Currently, we handle that with COPY instructions to and
> from the fixed registers, but that is making code motion passes more
> complicated than they need to be. (Actually, they usually just run
> away when they see one of these instructions).
>
> I would like to have MUL32r take two virtual register operands, one
> of them tied to the fixed register %EAX. Just like two-address
> instructions, it would be the register allocator's responsibility to
> satisfy the constraint. This would also make it possible to write
> proper isel patterns for MUL and DIV....
2013 Apr 25
0
[LLVMdev] [PATCH] Handle tied sub-operands in AsmMatcherEmitter
...tly, we handle that with COPY instructions to and
>> from the fixed registers, but that is making code motion passes more
>> complicated than they need to be. (Actually, they usually just run
>> away when they see one of these instructions).
>>
>> I would like to have MUL32r take two virtual register operands, one
>> of them tied to the fixed register %EAX. Just like two-address
>> instructions, it would be the register allocator's responsibility to
>> satisfy the constraint. This would also make it possible to write
>> proper isel patterns...
2013 Apr 24
0
[LLVMdev] [PATCH] Handle tied sub-operands in AsmMatcherEmitter
...DIV, take operands in fixed registers. Currently, we handle that with COPY instructions to and from the fixed registers, but that is making code motion passes more complicated than they need to be. (Actually, they usually just run away when they see one of these instructions).
I would like to have MUL32r take two virtual register operands, one of them tied to the fixed register %EAX. Just like two-address instructions, it would be the register allocator's responsibility to satisfy the constraint. This would also make it possible to write proper isel patterns for MUL and DIV.
This doesn't n...
2013 Apr 25
1
[LLVMdev] [PATCH] Handle tied sub-operands in AsmMatcherEmitter
...COPY instructions to and
> >> from the fixed registers, but that is making code motion passes more
> >> complicated than they need to be. (Actually, they usually just run
> >> away when they see one of these instructions).
> >>
> >> I would like to have MUL32r take two virtual register operands, one
> >> of them tied to the fixed register %EAX. Just like two-address
> >> instructions, it would be the register allocator's responsibility to
> >> satisfy the constraint. This would also make it possible to write
> >> p...
2009 Apr 13
1
[LLVMdev] Porting LLVM backend is no fun yet
Dan Gohman wrote:
> There certainly are wishlist items for TableGen and TableGen-based
> instruction descriptions, though I don't know of an official list.
> Offhand,
> a few things that come to mind are the ability to handle nodes with
> multiple results,
Is there an official workaround, BTW?
- Volodya
2018 Jul 10
2
Stuck with instruction in tablegen
2018 Jul 10
2
Stuck with instruction in tablegen
Hi,
I'm trying to revive jacobly0's Z80 back-end (from
https://github.com/jacobly0/llvm-z80) and build it with a current
version of LLVM.
Apart from some interface changes, I'm stuck at building the tables.
Specifically, the generation of the DAG instruction selector causes an
assertion in the table generator:
Assertion failed: Ops.size() >= NumSrcResults &&
2013 Apr 23
4
[LLVMdev] [PATCH] Handle tied sub-operands in AsmMatcherEmitter
Hi Ulrich,
Thank you for looking at this. Apologies again for taking unjustifiably long to get back to you. This is really good stuff and I very much want to see this go in. I like it enough I’m going to try to talk you into doing even more work on improving this code. ;)
Fair warning up front: You’re digging into some pretty fundamental problems in how the assemblers and code generators like to