search for: mul312

...; idx & (-8 | 7) -> idx After 155362 pattern #2 is deferred to DAGCombine stage, so InstCombine is unable to apply pattern #4: 4*. ((idx >> 3) << 3) | (idx & 7) -> idx // SimplifyOr can't handle it. So now LLVM IR contains a couple of redundant operations: %mul312 = shl nsw i32 %shr, 3 ; hi*8 %add313 = or i32 %mul312, %and ; hi*8 + lo == idx These few additional operations over index prevent our analysis pass from recognizing memory access patterns and I believe could harm not only us. I think 4* optimization can be safely done at LLVM IR level. Can you s...

...pattern #2 is deferred to DAGCombine stage, so InstCombine is > unable to apply pattern #4: > > 4*. ((idx >> 3) << 3) | (idx & 7) -> idx // SimplifyOr can’t handle > it. > > > > So now LLVM IR contains a couple of redundant operations: > > %mul312 = shl nsw i32 %shr, 3 ; hi*8 > > %add313 = or i32 %mul312, %and ; hi*8 + lo == idx > > > > These few additional operations over index prevent our analysis pass from > recognizing memory access patterns and I believe could harm not only us. > > I think 4* optimization ca...