Displaying 20 results from an estimated 21 matches for "mufu".
2017 Jun 27
4
[PATCH v4] nv110/exa: update sched codes
...8nv110.fp
index ce78036..101b67f 100644
--- a/src/shader/exac8nv110.fp
+++ b/src/shader/exac8nv110.fp
@@ -25,23 +25,23 @@ NV110FP_Composite_A8[] = {
};
#else
-sched (st 0x0) (st 0x0) (st 0x0)
+sched (st 0xf wr 0x0) (st 0xd wr 0x0 wt 0x1) (st 0xf wr 0x0 wt 0x1)
ipa pass $r0 a[0x7c] 0x0 0x0 0x1
mufu rcp $r0 $r0
ipa $r3 a[0x94] $r0 0x0 0x1
-sched (st 0x0) (st 0x0) (st 0x0)
+sched (st 0xf wr 0x1) (st 0xf wr 0x0 rd 0x1 wt 0x3) (st 0xf wr 0x1 wt 0x2)
ipa $r2 a[0x90] $r0 0x0 0x1
tex nodep $r1 $r2 0x0 0x1 t2d 0x8
ipa $r3 a[0x84] $r0 0x0 0x1
-sched (st 0x0) (st 0x0) (st 0x0)
+sched (st 0xf wr 0x2...
2017 Jun 10
2
[PATCH v3] nv110/exa: update sched codes
...8nv110.fp
index ce78036..101b67f 100644
--- a/src/shader/exac8nv110.fp
+++ b/src/shader/exac8nv110.fp
@@ -25,23 +25,23 @@ NV110FP_Composite_A8[] = {
};
#else
-sched (st 0x0) (st 0x0) (st 0x0)
+sched (st 0xf wr 0x0) (st 0xd wr 0x0 wt 0x1) (st 0xf wr 0x0 wt 0x1)
ipa pass $r0 a[0x7c] 0x0 0x0 0x1
mufu rcp $r0 $r0
ipa $r3 a[0x94] $r0 0x0 0x1
-sched (st 0x0) (st 0x0) (st 0x0)
+sched (st 0xf wr 0x1) (st 0xf wr 0x0 rd 0x1 wt 0x3) (st 0xf wr 0x1 wt 0x2)
ipa $r2 a[0x90] $r0 0x0 0x1
tex nodep $r1 $r2 0x0 0x1 t2d 0x8
ipa $r3 a[0x84] $r0 0x0 0x1
-sched (st 0x0) (st 0x0) (st 0x0)
+sched (st 0xf wr 0x2...
2017 Jun 03
2
[PATCH v2] nv110/exa: update sched codes
...8nv110.fp
index ce78036..1c4a4f1 100644
--- a/src/shader/exac8nv110.fp
+++ b/src/shader/exac8nv110.fp
@@ -25,23 +25,23 @@ NV110FP_Composite_A8[] = {
};
#else
-sched (st 0x0) (st 0x0) (st 0x0)
+sched (st 0xf wr 0x0) (st 0xd wr 0x0 wt 0x1) (st 0xf wr 0x0 wt 0x1)
ipa pass $r0 a[0x7c] 0x0 0x0 0x1
mufu rcp $r0 $r0
ipa $r3 a[0x94] $r0 0x0 0x1
-sched (st 0x0) (st 0x0) (st 0x0)
+sched (st 0xf wr 0x1) (st 0xf wr 0x0 rd 0x1 wt 0x3) (st 0xf wr 0x1 wt 0x2)
ipa $r2 a[0x90] $r0 0x0 0x1
tex nodep $r1 $r2 0x0 0x1 t2d 0x8
ipa $r3 a[0x84] $r0 0x0 0x1
-sched (st 0x0) (st 0x0) (st 0x0)
+sched (st 0xf wr 0x2...
2017 Jun 28
1
[PATCH v4] nv110/exa: update sched codes
...rc/shader/exac8nv110.fp
> > @@ -25,23 +25,23 @@ NV110FP_Composite_A8[] = {
> > };
> > #else
> >
> > -sched (st 0x0) (st 0x0) (st 0x0)
> > +sched (st 0xf wr 0x0) (st 0xd wr 0x0 wt 0x1) (st 0xf wr 0x0 wt 0x1)
> > ipa pass $r0 a[0x7c] 0x0 0x0 0x1
> > mufu rcp $r0 $r0
> > ipa $r3 a[0x94] $r0 0x0 0x1
> > -sched (st 0x0) (st 0x0) (st 0x0)
> > +sched (st 0xf wr 0x1) (st 0xf wr 0x0 rd 0x1 wt 0x3) (st 0xf wr 0x1 wt
> 0x2)
> > ipa $r2 a[0x90] $r0 0x0 0x1
> > tex nodep $r1 $r2 0x0 0x1 t2d 0x8
> > ipa $r3 a[0x84] $r...
2017 Jun 07
2
[PATCH v2] nv110/exa: update sched codes
...gt; +++ b/src/shader/exac8nv110.fp
>> @@ -25,23 +25,23 @@ NV110FP_Composite_A8[] = {
>> };
>> #else
>> -sched (st 0x0) (st 0x0) (st 0x0)
>> +sched (st 0xf wr 0x0) (st 0xd wr 0x0 wt 0x1) (st 0xf wr 0x0 wt 0x1)
>> ipa pass $r0 a[0x7c] 0x0 0x0 0x1
>> mufu rcp $r0 $r0
>> ipa $r3 a[0x94] $r0 0x0 0x1
>> -sched (st 0x0) (st 0x0) (st 0x0)
>> +sched (st 0xf wr 0x1) (st 0xf wr 0x0 rd 0x1 wt 0x3) (st 0xf wr 0x1 wt
>> 0x2)
>> ipa $r2 a[0x90] $r0 0x0 0x1
>> tex nodep $r1 $r2 0x0 0x1 t2d 0x8
>> ipa $r3 a[0x84]...
2018 Sep 08
0
[PATCH] maxwell,pascal: add scheduling data to shaders
...p
index ce78036..7537780 100644
--- a/src/shader/exac8nv110.fp
+++ b/src/shader/exac8nv110.fp
@@ -25,23 +25,24 @@ NV110FP_Composite_A8[] = {
};
#else
-sched (st 0x0) (st 0x0) (st 0x0)
+sched (st 0xf wr 0x0 wt 0x3f) (st 0xd wr 0x0 wt 0x1) (st 0x1 wr 0x0 wt 0x1)
ipa pass $r0 a[0x7c] 0x0 0x0 0x1
mufu rcp $r0 $r0
ipa $r3 a[0x94] $r0 0x0 0x1
-sched (st 0x0) (st 0x0) (st 0x0)
+sched (st 0xf wr 0x1) (st 0x2 wr 0x1 rd 0x0 wt 0x3) (st 0x1 wr 0x0 wt 0x1)
ipa $r2 a[0x90] $r0 0x0 0x1
tex nodep $r1 $r2 0x0 0x1 t2d 0x8
ipa $r3 a[0x84] $r0 0x0 0x1
-sched (st 0x0) (st 0x0) (st 0x0)
+sched (st 0xf wr 0x2...
2017 Jul 01
0
[PATCH v5 2/2] nv110/exa: update sched codes
...8nv110.fp
index 220d7e5..7797ef4 100644
--- a/src/shader/exac8nv110.fp
+++ b/src/shader/exac8nv110.fp
@@ -25,22 +25,22 @@ NV110FP_Composite_A8[] = {
};
#else
-sched (st 0x0) (st 0x0) (st 0x0)
+sched (st 0xf wr 0x0) (st 0xd wr 0x0 wt 0x1) (st 0xf wr 0x0 wt 0x1)
ipa pass $r0 a[0x7c] 0x0 0x0 0x1
mufu rcp $r0 $r0
ipa $r3 a[0x94] $r0 0x0 0x1
-sched (st 0x0) (st 0x0) (st 0x0)
+sched (st 0xf wr 0x1) (st 0xf wr 0x0 wt 0x3) (st 0xf wr 0x0 wt 0x1)
ipa $r2 a[0x90] $r0 0x0 0x1
tex nodep $r1 $r2 0x0 0x1 t2d 0x8
ipa $r3 a[0x84] $r0 0x0 0x1
-sched (st 0x0) (st 0x0) (st 0x0)
+sched (st 0xf wr 0x1) (st 0...
2017 Jun 03
0
[PATCH] nv110/exa: update sched codes
...8nv110.fp
index ce78036..1c4a4f1 100644
--- a/src/shader/exac8nv110.fp
+++ b/src/shader/exac8nv110.fp
@@ -25,23 +25,23 @@ NV110FP_Composite_A8[] = {
};
#else
-sched (st 0x0) (st 0x0) (st 0x0)
+sched (st 0xf wr 0x0) (st 0xd wr 0x0 wt 0x1) (st 0xf wr 0x0 wt 0x1)
ipa pass $r0 a[0x7c] 0x0 0x0 0x1
mufu rcp $r0 $r0
ipa $r3 a[0x94] $r0 0x0 0x1
-sched (st 0x0) (st 0x0) (st 0x0)
+sched (st 0xf wr 0x1) (st 0xf wr 0x0 rd 0x1 wt 0x3) (st 0xf wr 0x1 wt 0x2)
ipa $r2 a[0x90] $r0 0x0 0x1
tex nodep $r1 $r2 0x0 0x1 t2d 0x8
ipa $r3 a[0x84] $r0 0x0 0x1
-sched (st 0x0) (st 0x0) (st 0x0)
+sched (st 0xf wr 0x2...
2017 Jun 29
0
[PATCH v4] nv110/exa: update sched codes
...shader/exac8nv110.fp
> +++ b/src/shader/exac8nv110.fp
> @@ -25,23 +25,23 @@ NV110FP_Composite_A8[] = {
> };
> #else
>
> -sched (st 0x0) (st 0x0) (st 0x0)
> +sched (st 0xf wr 0x0) (st 0xd wr 0x0 wt 0x1) (st 0xf wr 0x0 wt 0x1)
> ipa pass $r0 a[0x7c] 0x0 0x0 0x1
> mufu rcp $r0 $r0
> ipa $r3 a[0x94] $r0 0x0 0x1
> -sched (st 0x0) (st 0x0) (st 0x0)
> +sched (st 0xf wr 0x1) (st 0xf wr 0x0 rd 0x1 wt 0x3) (st 0xf wr 0x1 wt 0x2)
> ipa $r2 a[0x90] $r0 0x0 0x1
> tex nodep $r1 $r2 0x0 0x1 t2d 0x8
> ipa $r3 a[0x84] $r0 0x0 0x1
> -sched (st 0x0)...
2017 Jun 10
0
[PATCH v3] nv110/exa: update sched codes
...a/src/shader/exac8nv110.fp
> +++ b/src/shader/exac8nv110.fp
> @@ -25,23 +25,23 @@ NV110FP_Composite_A8[] = {
> };
> #else
>
> -sched (st 0x0) (st 0x0) (st 0x0)
> +sched (st 0xf wr 0x0) (st 0xd wr 0x0 wt 0x1) (st 0xf wr 0x0 wt 0x1)
> ipa pass $r0 a[0x7c] 0x0 0x0 0x1
> mufu rcp $r0 $r0
> ipa $r3 a[0x94] $r0 0x0 0x1
> -sched (st 0x0) (st 0x0) (st 0x0)
> +sched (st 0xf wr 0x1) (st 0xf wr 0x0 rd 0x1 wt 0x3) (st 0xf wr 0x1 wt 0x2)
> ipa $r2 a[0x90] $r0 0x0 0x1
> tex nodep $r1 $r2 0x0 0x1 t2d 0x8
> ipa $r3 a[0x84] $r0 0x0 0x1
> -sched (st 0x0) (st...
2017 Jun 28
0
[PATCH v4] nv110/exa: update sched codes
...a/src/shader/exac8nv110.fp
> +++ b/src/shader/exac8nv110.fp
> @@ -25,23 +25,23 @@ NV110FP_Composite_A8[] = {
> };
> #else
>
> -sched (st 0x0) (st 0x0) (st 0x0)
> +sched (st 0xf wr 0x0) (st 0xd wr 0x0 wt 0x1) (st 0xf wr 0x0 wt 0x1)
> ipa pass $r0 a[0x7c] 0x0 0x0 0x1
> mufu rcp $r0 $r0
> ipa $r3 a[0x94] $r0 0x0 0x1
> -sched (st 0x0) (st 0x0) (st 0x0)
> +sched (st 0xf wr 0x1) (st 0xf wr 0x0 rd 0x1 wt 0x3) (st 0xf wr 0x1 wt 0x2)
> ipa $r2 a[0x90] $r0 0x0 0x1
> tex nodep $r1 $r2 0x0 0x1 t2d 0x8
> ipa $r3 a[0x84] $r0 0x0 0x1
> -sched (st 0x0) (st...
2017 Jul 01
2
[PATCH 1/2] nv110/exa: Remove depbars
Removed explicit depar instructions as they're not used by the blob anymore.
Signed-off-by: Aaryaman Vasishta <jem456.vasishta at gmail.com>
---
src/shader/exac8nv110.fp | 5 ++---
src/shader/exac8nv110.fpc | 10 ++++------
src/shader/exacanv110.fp | 5 ++---
src/shader/exacanv110.fpc | 10 ++++------
src/shader/exacmnv110.fp | 5 ++---
src/shader/exacmnv110.fpc | 10 ++++------
2017 Jun 05
0
[PATCH v2] nv110/exa: update sched codes
...shader/exac8nv110.fp
> +++ b/src/shader/exac8nv110.fp
> @@ -25,23 +25,23 @@ NV110FP_Composite_A8[] = {
> };
> #else
>
> -sched (st 0x0) (st 0x0) (st 0x0)
> +sched (st 0xf wr 0x0) (st 0xd wr 0x0 wt 0x1) (st 0xf wr 0x0 wt 0x1)
> ipa pass $r0 a[0x7c] 0x0 0x0 0x1
> mufu rcp $r0 $r0
> ipa $r3 a[0x94] $r0 0x0 0x1
> -sched (st 0x0) (st 0x0) (st 0x0)
> +sched (st 0xf wr 0x1) (st 0xf wr 0x0 rd 0x1 wt 0x3) (st 0xf wr 0x1 wt 0x2)
> ipa $r2 a[0x90] $r0 0x0 0x1
> tex nodep $r1 $r2 0x0 0x1 t2d 0x8
> ipa $r3 a[0x84] $r0 0x0 0x1
> -sched (st 0x0)...
2017 Jun 08
1
[PATCH v2] nv110/exa: update sched codes
...@ NV110FP_Composite_A8[] = {
>> };
>> #else
>> -sched (st 0x0) (st 0x0) (st 0x0)
>> +sched (st 0xf wr 0x0) (st 0xd wr 0x0 wt 0x1) (st 0xf wr 0x0 wt
>> 0x1)
>> ipa pass $r0 a[0x7c] 0x0 0x0 0x1
>> mufu rcp $r0 $r0
>> ipa $r3 a[0x94] $r0 0x0 0x1
>> -sched (st 0x0) (st 0x0) (st 0x0)
>> +sched (st 0xf wr 0x1) (st 0xf wr 0x0 rd 0x1 wt 0x3) (st 0xf wr
>> 0x1 wt 0x2)
>> ipa $r2 a[0x90] $r0 0x0 0x1
>> tex nodep...
2017 Jun 07
0
[PATCH v2] nv110/exa: update sched codes
...p
> @@ -25,23 +25,23 @@ NV110FP_Composite_A8[] = {
> };
> #else
> -sched (st 0x0) (st 0x0) (st 0x0)
> +sched (st 0xf wr 0x0) (st 0xd wr 0x0 wt 0x1) (st 0xf wr 0x0 wt 0x1)
> ipa pass $r0 a[0x7c] 0x0 0x0 0x1
> mufu rcp $r0 $r0
> ipa $r3 a[0x94] $r0 0x0 0x1
> -sched (st 0x0) (st 0x0) (st 0x0)
> +sched (st 0xf wr 0x1) (st 0xf wr 0x0 rd 0x1 wt 0x3) (st 0xf wr
> 0x1 wt 0x2)
> ipa $r2 a[0x90] $r0 0x0 0x1
> tex nodep $r1 $r2 0x0 0x1 t2d 0x8...
2017 Jun 12
2
[PATCH v3] nv110/exa: update sched codes
...+++ b/src/shader/exac8nv110.fp
> @@ -25,23 +25,23 @@ NV110FP_Composite_A8[] = {
> };
> #else
>
> -sched (st 0x0) (st 0x0) (st 0x0)
> +sched (st 0xf wr 0x0) (st 0xd wr 0x0 wt 0x1) (st 0xf wr 0x0 wt 0x1)
> ipa pass $r0 a[0x7c] 0x0 0x0 0x1
> mufu rcp $r0 $r0
> ipa $r3 a[0x94] $r0 0x0 0x1
> -sched (st 0x0) (st 0x0) (st 0x0)
> +sched (st 0xf wr 0x1) (st 0xf wr 0x0 rd 0x1 wt 0x3) (st 0xf wr 0x1
> wt 0x2)
> ipa $r2 a[0x90] $r0 0x0 0x1
> tex nodep $r1 $r2 0x0 0x1 t2d 0x8
> ipa $r3 a[0x84]...
2016 Oct 16
2
[PATCH] exa: add GM10x acceleration support
...0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x0000000f,
+ 0x00000000,
+#include "exac8nv110.fpc"
+};
+#else
+
+sched (st 0x0) (st 0x0) (st 0x0)
+ipa pass $r0 a[0x7c] 0x0 0x0 0x1
+mufu rcp $r0 $r0
+ipa $r3 a[0x94] $r0 0x0 0x1
+sched (st 0x0) (st 0x0) (st 0x0)
+ipa $r2 a[0x90] $r0 0x0 0x1
+tex nodep $r1 $r2 0x0 0x1 t2d 0x8
+ipa $r3 a[0x84] $r0 0x0 0x1
+sched (st 0x0) (st 0x0) (st 0x0)
+ipa $r2 a[0x80] $r0 0x0 0x1
+tex nodep $r0 $r2 0x0 0x0 t2d 0x8
+depbar le 0x5 0x0 0x0
+sched (st...
2016 Oct 27
0
[PATCH v2 1/7] exa: add GM10x acceleration support
...0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x0000000f,
+ 0x00000000,
+#include "exac8nv110.fpc"
+};
+#else
+
+sched (st 0x0) (st 0x0) (st 0x0)
+ipa pass $r0 a[0x7c] 0x0 0x0 0x1
+mufu rcp $r0 $r0
+ipa $r3 a[0x94] $r0 0x0 0x1
+sched (st 0x0) (st 0x0) (st 0x0)
+ipa $r2 a[0x90] $r0 0x0 0x1
+tex nodep $r1 $r2 0x0 0x1 t2d 0x8
+ipa $r3 a[0x84] $r0 0x0 0x1
+sched (st 0x0) (st 0x0) (st 0x0)
+ipa $r2 a[0x80] $r0 0x0 0x1
+tex nodep $r0 $r2 0x0 0x0 t2d 0x8
+depbar le 0x5 0x0 0x0
+sched (st...
2015 Feb 20
10
[PATCH 01/11] nvc0/ir: add emission of dadd/dmul/dmad opcodes, fix minmax
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
.../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 66 +++++++++++++++++++++-
1 file changed, 63 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index dfb093c..e38a3b8 100644
---
2016 Oct 17
0
[PATCH] exa: add GM10x acceleration support
...00000000,
> +#include "exac8nv110.fpc"
> +};
> +#else
> +
> +sched (st 0x0) (st 0x0) (st 0x0)
Those sched codes are definitely bad, but let's keep them as it for now.
I might have a look at some point to improve the thing.
> +ipa pass $r0 a[0x7c] 0x0 0x0 0x1
> +mufu rcp $r0 $r0
> +ipa $r3 a[0x94] $r0 0x0 0x1
> +sched (st 0x0) (st 0x0) (st 0x0)
> +ipa $r2 a[0x90] $r0 0x0 0x1
> +tex nodep $r1 $r2 0x0 0x1 t2d 0x8
> +ipa $r3 a[0x84] $r0 0x0 0x1
> +sched (st 0x0) (st 0x0) (st 0x0)
> +ipa $r2 a[0x80] $r0 0x0 0x1
> +tex nodep $r0 $r2 0x0 0x0 t...