search for: msub

.../export/home/example/Runs/eg.RData") mpi.quit(save = "no") ---------------------------------------------------------------------------------------------------- eg.sh code ---------------------------------------------------------------------------------------------------- #MSUB -l nodes=1:ppn=1 #MSUB -l walltime=100:00:00 #MSUB -m be #MSUB -V #MSUB -o /export/home/example/Runs/eg.out #MSUB -e /export/home/example/Runs/eg.err #MSUB -d /export/home/example/Runs mpirun --mca mpi_warn_on_fork 0 -np 1 /export/home/R-2.12.1/bin/R --slave -f /export/home/example/Runs/eg.r ech...

Hello, I'm new on this list. First of all, thank you to all the developers of this great project! At the moment there is only an application that keeps me on both macos and windows, its name is PWGL a free environment for computer assisted composition in openGL. (http://www2.siba.fi/PWGL/) I'm running Ubuntu 8.04 and wine 0.9.59. I have to say that I also installed vcrun2005 and

Hi, Jim. In my case the target (Tilera) doesn't have a full 32-bit mult operation and to do so it has to accumulate results from three 16-bit mults, by retaining operands and the result across in the same registers. However the ISel DAG thinks its a CSE case. Please note this is not a MAdd/MSub triad. How could I do this by defining such a sequence or the pattern in the .def file itself for the ISD::MUL? Thanks. Girish. >________________________________ > From: Jim Grosbach <grosbach at apple.com> >To: girish gulawani <girishvg at yahoo.com> >Cc: Johannes Birgm...

...Hi, Jim. > In my case the target (Tilera) doesn't have a full 32-bit mult operation and to do so it has to accumulate results from three 16-bit mults, by retaining operands and the result across in the same registers. However the ISel DAG thinks its a CSE case. Please note this is not a MAdd/MSub triad. > > How could I do this by defining such a sequence or the pattern in the .def file itself for the ISD::MUL? > Thanks. > Girish. > > From: Jim Grosbach <grosbach at apple.com> > To: girish gulawani <girishvg at yahoo.com> > Cc: Johannes Birgmeier <e0...

...Jim. >>In my case the target (Tilera) doesn't have a full 32-bit mult operation and to do so it has to accumulate results from three 16-bit mults, by retaining operands and the result across in the same registers. However the ISel DAG thinks its a CSE case. Please note this is not a MAdd/MSub triad. >> >> >>How could I do this by defining such a sequence or the pattern in the .def file itself for the ISD::MUL? >>Thanks. >>Girish. >> >> >> >>>________________________________ >>> From: Jim Grosbach <grosbach at apple.com...

Hi Girish, Sorry, but I'm afraid I don't understand your question. Can you elaborate a bit? -Jim On Dec 19, 2011, at 9:12 PM, girish gulawani wrote: > > Hello Jim. > Just out of curiosity, won't such mechanism work via the patterns from instructions defs? > > Thanks. > Girish. > > From: Jim Grosbach <grosbach at apple.com> > To: Johannes

Hello Jim. Just out of curiosity, won't such mechanism work via the patterns from instructions defs? Thanks. Girish. >________________________________ > From: Jim Grosbach <grosbach at apple.com> >To: Johannes Birgmeier <e0902998 at student.tuwien.ac.at> >Cc: LLVM Developers Mailing List <llvmdev at cs.uiuc.edu> >Sent: Monday, 19 December 2011 10:33 PM