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...version is: > > Default target: x86_64-unknown-linux-gnu > Host CPU: haswell > > So, what we currently do is use the default target (which is normally the > host target), but ignore the host cpu? > > Michael > > On Wed, Nov 30, 2016 at 10:58 AM, Matthew Simpson <mssimpso at codeaurora.org > > wrote: > >> >> On Wed, Nov 30, 2016 at 1:04 PM, Michael Kuperstein via llvm-dev < >> llvm-dev at lists.llvm.org> wrote: >> >>> So, just to make sure I understand, what is getting a specific TTI in >>> llc triggered off?...

...see how it (mis)behaves. From: Michael Kuperstein [mailto:mkuper at google.com] Sent: Thursday, August 18, 2016 03:57 To: Zaks, Ayal <ayal.zaks at intel.com> Cc: Demikhovsky, Elena <elena.demikhovsky at intel.com>; Renato Golin <renato.golin at linaro.org>; Matthew Simpson <mssimpso at codeaurora.org>; Nema, Ashutosh <Ashutosh.Nema at amd.com>; Sanjay Patel <spatel at rotateright.com>; llvm-dev <llvm-dev at lists.llvm.org> Subject: Re: [llvm-dev] enabling interleaved access loop vectorization So, at least for this example, it looks like we actually want t...

----- Original Message ----- > From: "Arnold Schwaighofer via llvm-dev" <llvm-dev at lists.llvm.org> > To: "Matthew Simpson" <mssimpso at codeaurora.org> > Cc: "llvm-dev" <llvm-dev at lists.llvm.org> > Sent: Tuesday, December 13, 2016 9:17:08 AM > Subject: Re: [llvm-dev] Enabling scalarized conditional stores in the loop vectorizer > > I added this feature for libquantum > (http://llvm.org/vie...

...Michael Kuperstein [mailto:mkuper at google.com] > *Sent:* Wednesday, August 17, 2016 00:51 > *To:* Zaks, Ayal <ayal.zaks at intel.com>; Demikhovsky, Elena < > elena.demikhovsky at intel.com> > *Cc:* Renato Golin <renato.golin at linaro.org>; Matthew Simpson < > mssimpso at codeaurora.org>; Nema, Ashutosh <Ashutosh.Nema at amd.com>; Sanjay > Patel <spatel at rotateright.com>; llvm-dev <llvm-dev at lists.llvm.org> > > *Subject:* Re: [llvm-dev] enabling interleaved access loop vectorization > > > > Hi Ayal, Elena, > > &...

...e the case what Matt described here. I will take a look at it. Farhana From: Michael Kuperstein [mailto:mkuper at google.com] Sent: Wednesday, December 14, 2016 9:56 AM To: Das, Dibyendu <Dibyendu.Das at amd.com>; Aleen, Farhana A <farhana.a.aleen at intel.com> Cc: Matthew Simpson <mssimpso at codeaurora.org>; llvm-dev at lists.llvm.org Subject: Re: [llvm-dev] Enabling scalarized conditional stores in the loop vectorizer I haven't verified what Matt described is what actually happens, but assuming it is - that is a known issue in the x86 cost model. Vectorizing interleaved me...

...point - Hal enabled it on PPC last September. An important difference vs. x86 seems to be that arbitrary shuffles are cheap on PPC, but, as I said below, I hope we can enable it on x86 with a conservative cost function, and still get improvement. On Fri, Aug 5, 2016 at 7:02 AM, Matthew Simpson <mssimpso at codeaurora.org> wrote: > Isn't our current interleaved access vectorization just a special case of > the more general strided access proposal? If so, from a development > perspective, it might make sense to begin incorporating some of that work > into the existing framework (...

Yeah, this makes a lot of sense, -mcpu=generic (as opposed to -mcpu=native) is the sane default. I guess I was just expecting an x86 host to get a "generic x86 TTI" (whatever that means), not a "generic TTI". On Wed, Nov 30, 2016 at 11:49 AM, Matthew Simpson <mssimpso at codeaurora.org> wrote: > That's right. In your example, if the target isn't specified anywhere, an > llc invocation would be equivalent to "llc -mtriple=x86_64-unknown-linux-gnu > -mcpu=generic". TTI queries (in e.g., CodeGenPrepare) would be based on > this. Fr...

...>>> >>> >>> >>> *From:* Demikhovsky, Elena >>> *Sent:* Monday, August 08, 2016 00:09 >>> *To:* Michael Kuperstein <mkuper at google.com>; Renato Golin < >>> renato.golin at linaro.org> >>> *Cc:* Matthew Simpson <mssimpso at codeaurora.org>; Nema, Ashutosh < >>> Ashutosh.Nema at amd.com>; Sanjay Patel <spatel at rotateright.com>; llvm-dev >>> <llvm-dev at lists.llvm.org>; Zaks, Ayal <ayal.zaks at intel.com> >>> *Subject:* RE: [llvm-dev] enabling interleaved acces...

...s feature for libquantum (http://llvm.org/viewvc/llvm-project?view=revision&revision=200270) waiting for an update to the cost model modeling the scalarization of stores which you recently added. Assuming no serious regressions this SGTM. > On Dec 13, 2016, at 5:41 AM, Matthew Simpson <mssimpso at codeaurora.org> wrote: > > Hi Michael, > > Thanks for testing this on your benchmarks and target. I think the results will help guide the direction we go. I tested the feature with spec2k/2k6 on AArch64/Kryo and saw minor performance swings, aside from a large (30%) improvement...

...in 32-bit mode. The 64-bit mode looks good overall. - Elena From: Michael Kuperstein [mailto:mkuper at google.com] Sent: Saturday, August 06, 2016 02:56 To: Renato Golin <renato.golin at linaro.org> Cc: Demikhovsky, Elena <elena.demikhovsky at intel.com>; Matthew Simpson <mssimpso at codeaurora.org>; Nema, Ashutosh <Ashutosh.Nema at amd.com>; Sanjay Patel <spatel at rotateright.com>; llvm-dev <llvm-dev at lists.llvm.org>; Zaks, Ayal <ayal.zaks at intel.com> Subject: Re: [llvm-dev] enabling interleaved access loop vectorization On Fri, Aug 5, 201...

...Michael On Wed, Dec 14, 2016 at 8:44 AM, Das, Dibyendu <Dibyendu.Das at amd.com> wrote: > Hi Matt- > > > > Yeah I used a pretty recent llvm (post 3.9) on an x86-64 ( both AMD and > Intel ). > > > > -dibyendu > > > > *From:* Matthew Simpson [mailto:mssimpso at codeaurora.org] > *Sent:* Wednesday, December 14, 2016 10:03 PM > *To:* Das, Dibyendu <Dibyendu.Das at amd.com> > *Cc:* Michael Kuperstein <mkuper at google.com>; llvm-dev at lists.llvm.org > > *Subject:* Re: [llvm-dev] Enabling scalarized conditional stores in the &gt...

...), > is DENBench’s RGB conversions. > > > > Ayal. > > > > *From:* Demikhovsky, Elena > *Sent:* Monday, August 08, 2016 00:09 > *To:* Michael Kuperstein <mkuper at google.com>; Renato Golin < > renato.golin at linaro.org> > *Cc:* Matthew Simpson <mssimpso at codeaurora.org>; Nema, Ashutosh < > Ashutosh.Nema at amd.com>; Sanjay Patel <spatel at rotateright.com>; llvm-dev < > llvm-dev at lists.llvm.org>; Zaks, Ayal <ayal.zaks at intel.com> > *Subject:* RE: [llvm-dev] enabling interleaved access loop vectorization &g...

...s? Do you know of > specific targets where the cost model is known to be good enough, so it's > clearly beneficial? > > (+Arnold, who probably knows why this is disabled by default. :-) ) > > Thanks, > Michael > > On Mon, Dec 12, 2016 at 2:52 PM, Matthew Simpson <mssimpso at codeaurora.org> > wrote: > >> Hi, >> >> I'd like to enable the scalarized conditional stores feature in the loop >> vectorizer (-enable-cond-stores-vec=true). The feature allows us to >> vectorize loops containing conditional stores that must be scalari...

...is makes a lot of sense, -mcpu=generic (as opposed to > -mcpu=native) is the sane default. > I guess I was just expecting an x86 host to get a "generic x86 TTI" > (whatever that means), not a "generic TTI". > > On Wed, Nov 30, 2016 at 11:49 AM, Matthew Simpson <mssimpso at codeaurora.org > > wrote: > >> That's right. In your example, if the target isn't specified anywhere, an >> llc invocation would be equivalent to "llc -mtriple=x86_64-unknown-linux-gnu >> -mcpu=generic". TTI queries (in e.g., CodeGenPrepare) would be...

Hi Matt- Yeah I used a pretty recent llvm (post 3.9) on an x86-64 ( both AMD and Intel ). -dibyendu From: Matthew Simpson [mailto:mssimpso at codeaurora.org] Sent: Wednesday, December 14, 2016 10:03 PM To: Das, Dibyendu <Dibyendu.Das at amd.com> Cc: Michael Kuperstein <mkuper at google.com>; llvm-dev at lists.llvm.org Subject: Re: [llvm-dev] Enabling scalarized conditional stores in the loop vectorizer Hi Dibyendu, Are y...

...yendu.Das at amd.com> > wrote: > >> Hi Matt- >> >> >> >> Yeah I used a pretty recent llvm (post 3.9) on an x86-64 ( both AMD and >> Intel ). >> >> >> >> -dibyendu >> >> >> >> *From:* Matthew Simpson [mailto:mssimpso at codeaurora.org] >> *Sent:* Wednesday, December 14, 2016 10:03 PM >> *To:* Das, Dibyendu <Dibyendu.Das at amd.com> >> *Cc:* Michael Kuperstein <mkuper at google.com>; llvm-dev at lists.llvm.org >> >> *Subject:* Re: [llvm-dev] Enabling scalarized condition...

...gt; > From: Andrew Trick via llvm-commits <llvm-commits at lists.llvm.org> > Subject: Re: [PATCH] D20695: Floating Point SCEV Analysis > Date: May 30, 2016 at 11:05:35 AM PDT > To: reviews+D20695+public+faa7820b5ed6aa91 at reviews.llvm.org > Cc: llvm-commits at lists.llvm.org, mssimpso at codeaurora.org > Reply-To: Andrew Trick <atrick at apple.com> > > >> On May 30, 2016, at 12:02 AM, Sanjoy Das <sanjoy at playingwithpointers.com <mailto:sanjoy at playingwithpointers.com>> wrote: >> >> I have made some minor comments inline, but I...

Right, let's say what we get from llc --version is: Default target: x86_64-unknown-linux-gnu Host CPU: haswell So, what we currently do is use the default target (which is normally the host target), but ignore the host cpu? Michael On Wed, Nov 30, 2016 at 10:58 AM, Matthew Simpson <mssimpso at codeaurora.org> wrote: > > On Wed, Nov 30, 2016 at 1:04 PM, Michael Kuperstein via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> So, just to make sure I understand, what is getting a specific TTI in llc >> triggered off? -mcpu? > > > Right, TTI w...

...uggestions, however, welcome! ---------- Forwarded message ---------- From: Renato Golin <renato.golin at linaro.org> Date: Fri, Oct 30, 2015 at 10:15 AM Subject: Re: [PATCH] D13259: LLE 6/6: Add LoopLoadElimination pass To: anemet at apple.com, hfinkel at anl.gov, dberlin at dberlin.org Cc: mssimpso at codeaurora.org, sanjoy at playingwithpointers.com, llvm-commits at lists.llvm.org rengolin added a comment. In http://reviews.llvm.org/D13259#278362, @dberlin wrote: > I would suggest rather than prefix *anything*, anywhere, that if we want > prefixes, we just have the DEBUG macro out...

...gets where the cost model is known to be good enough, so it's > clearly beneficial? > > > > (+Arnold, who probably knows why this is disabled by default. :-) ) > > > > Thanks, > > Michael > > > > On Mon, Dec 12, 2016 at 2:52 PM, Matthew Simpson <mssimpso at codeaurora.org> > wrote: > > Hi, > > > > I'd like to enable the scalarized conditional stores feature in the loop > vectorizer (-enable-cond-stores-vec=true). The feature allows us to > vectorize loops containing conditional stores that must be scalarized and &g...