Displaying 17 results from an estimated 17 matches for "msr_type_w".
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msr_type_rw
2013 Jan 29
3
[PATCH v4 2/2] Xen: Fix VMCS setting for x2APIC mode guest while enabling APICV
..._for_msr(struct vcpu *v, u32 msr, int type)
if ( msr <= 0x1fff )
{
if (type & MSR_TYPE_R)
- __clear_bit(msr, msr_bitmap + 0x000/BYTES_PER_LONG); /* read-low */
+ clear_bit(msr, msr_bitmap + 0x000/BYTES_PER_LONG); /* read-low */
if (type & MSR_TYPE_W)
- __clear_bit(msr, msr_bitmap + 0x800/BYTES_PER_LONG); /* write-low */
+ clear_bit(msr, msr_bitmap + 0x800/BYTES_PER_LONG); /* write-low */
}
else if ( (msr >= 0xc0000000) && (msr <= 0xc0001fff) )
{
msr &= 0x1fff;
if (type &a...
2020 Jul 21
0
[PATCH v9 17/84] KVM: x86: use MSR_TYPE_R, MSR_TYPE_W and MSR_TYPE_RW with AMD
.../asm/kvm_host.h
index 6be832ba9c97..a3230ab377db 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -140,6 +140,10 @@ static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level)
#define CR_TYPE_W 2
#define CR_TYPE_RW 3
+#define MSR_TYPE_R 1
+#define MSR_TYPE_W 2
+#define MSR_TYPE_RW 3
+
#define ASYNC_PF_PER_VCPU 64
enum kvm_reg {
diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
index 4e5b07606891..e16be80edd7e 100644
--- a/arch/x86/kvm/svm/svm.c
+++ b/arch/x86/kvm/svm/svm.c
@@ -584,7 +584,7 @@ static bool msr_write_intercepted(struct kvm_...
2020 Feb 07
0
[RFC PATCH v7 16/78] KVM: x86: use MSR_TYPE_R, MSR_TYPE_W and MSR_TYPE_RW with AMD code too
.../asm/kvm_host.h
index 8cdb6cece618..2136f273645a 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -138,6 +138,10 @@ static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level)
#define CR_TYPE_W 2
#define CR_TYPE_RW 3
+#define MSR_TYPE_R 1
+#define MSR_TYPE_W 2
+#define MSR_TYPE_RW 3
+
#define ASYNC_PF_PER_VCPU 64
enum kvm_reg {
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index e3369562d6fe..0021d8c2feca 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -1078,7 +1078,7 @@ static bool msr_write_intercepted(struct kvm_vcpu *vcpu, un...
2013 Nov 14
2
[PATCH] x86/VT-x: Disable MSR intercept for SHADOW_GS_BASE.
...iff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c
index 290b42f..4aab971 100644
--- a/xen/arch/x86/hvm/vmx/vmcs.c
+++ b/xen/arch/x86/hvm/vmx/vmcs.c
@@ -950,6 +950,7 @@ static int construct_vmcs(struct vcpu *v)
vmx_disable_intercept_for_msr(v, MSR_FS_BASE, MSR_TYPE_R | MSR_TYPE_W);
vmx_disable_intercept_for_msr(v, MSR_GS_BASE, MSR_TYPE_R | MSR_TYPE_W);
+ vmx_disable_intercept_for_msr(v, MSR_SHADOW_GS_BASE, MSR_TYPE_R | MSR_TYPE_W);
vmx_disable_intercept_for_msr(v, MSR_IA32_SYSENTER_CS, MSR_TYPE_R | MSR_TYPE_W);
vmx_disable_intercept_for_msr...
2020 Feb 07
0
[RFC PATCH v7 70/78] KVM: introspection: restore the state of MSR interception on unhook
...gned int msr_mask_to_base(struct kvm_vcpu *vcpu, unsigned long *mask)
return 0;
}
+static void kvmi_control_msrw_intercept(struct kvm_vcpu *vcpu, u32 msr,
+ bool enable)
+{
+ vcpu->arch.kvmi->msrw.monitor_fct = monitor_msrw_fct_kvmi;
+ kvm_x86_ops->control_msr_intercept(vcpu, msr, MSR_TYPE_W, enable);
+ vcpu->arch.kvmi->msrw.monitor_fct = monitor_msrw_fct_kvm;
+}
+
static void kvmi_arch_disable_msr_intercept(struct kvm_vcpu *vcpu,
unsigned long *mask)
{
@@ -427,9 +513,7 @@ static void kvmi_arch_disable_msr_intercept(struct kvm_vcpu *vcpu,
if (offset >= KVMI_NUM_...
2020 Feb 07
0
[RFC PATCH v7 18/78] KVM: vmx: pass struct kvm_vcpu to the intercept msr related functions
...YPE_RW);
break;
@@ -2050,8 +2051,8 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
* vmcs02.msr_bitmap here since it gets completely overwritten
* in the merging.
*/
- vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
- MSR_TYPE_W);
+ vmx_disable_intercept_for_msr(vcpu, vmx->vmcs01.msr_bitmap,
+ MSR_IA32_PRED_CMD, MSR_TYPE_W);
break;
case MSR_IA32_CR_PAT:
if (!kvm_pat_valid(data))
@@ -3612,7 +3613,8 @@ void free_vpid(int vpid)
spin_unlock(&vmx_vpid_lock);
}
-static __always_inline void vmx_disa...
2020 Jul 21
0
[PATCH v9 19/84] KVM: vmx: pass struct kvm_vcpu to the intercept msr related functions
...YPE_RW);
break;
@@ -2122,8 +2123,8 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
* vmcs02.msr_bitmap here since it gets completely overwritten
* in the merging.
*/
- vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
- MSR_TYPE_W);
+ vmx_disable_intercept_for_msr(vcpu, vmx->vmcs01.msr_bitmap,
+ MSR_IA32_PRED_CMD, MSR_TYPE_W);
break;
case MSR_IA32_CR_PAT:
if (!kvm_pat_valid(data))
@@ -3733,7 +3734,8 @@ void free_vpid(int vpid)
spin_unlock(&vmx_vpid_lock);
}
-static __always_inline void vmx_disa...
2013 Dec 02
0
[PATCH v4 3/7] X86: MPX IA32_BNDCFGS msr handle
...ENTRY_LOAD_BNDCFGS;
_vmx_vmentry_control = adjust_vmx_controls(
"VMEntry Control", min, opt, MSR_IA32_VMX_ENTRY_CTLS, &mismatch);
@@ -955,6 +956,9 @@ static int construct_vmcs(struct vcpu *v)
vmx_disable_intercept_for_msr(v, MSR_IA32_SYSENTER_EIP, MSR_TYPE_R | MSR_TYPE_W);
if ( paging_mode_hap(d) && (!iommu_enabled || iommu_snoop) )
vmx_disable_intercept_for_msr(v, MSR_IA32_CR_PAT, MSR_TYPE_R | MSR_TYPE_W);
+ if ( (vmexit_ctl & VM_EXIT_CLEAR_BNDCFGS) &&
+ (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS) )
+...
2020 Feb 07
0
[RFC PATCH v7 17/78] KVM: svm: pass struct kvm_vcpu to set_msr_interception()
...srl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
if (is_guest_mode(vcpu))
break;
- set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD,
+ set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PRED_CMD,
+ MSR_TYPE_R, 0);
+ set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PRED_CMD,
MSR_TYPE_W, 1);
break;
case MSR_AMD64_VIRT_SPEC_CTRL:
2020 Feb 07
0
[RFC PATCH v7 69/78] KVM: introspection: add KVMI_VCPU_CONTROL_MSR and KVMI_EVENT_MSR
...unsigned long *mask)
+{
+ int offset = -1;
+ unsigned int msr_base = msr_mask_to_base(vcpu, mask);
+
+ for (;;) {
+ offset = find_next_bit(mask, KVMI_NUM_MSR, offset + 1);
+
+ if (offset >= KVMI_NUM_MSR)
+ break;
+
+ kvm_x86_ops->control_msr_intercept(vcpu, msr_base + offset,
+ MSR_TYPE_W, false);
+ msr_control(vcpu, msr_base + offset, false);
+ }
+
+ bitmap_zero(mask, KVMI_NUM_MSR);
+}
+
int kvmi_arch_cmd_control_intercept(struct kvm_vcpu *vcpu,
unsigned int event_id, bool enable)
{
@@ -418,6 +484,8 @@ bool kvmi_arch_restore_interception(struct kvm_vcpu *vcpu)
kvmi_ar...
2020 Jul 21
0
[PATCH v9 75/84] KVM: introspection: add KVMI_VCPU_CONTROL_MSR and KVMI_EVENT_MSR
...unsigned long *mask)
+{
+ unsigned int msr_base = msr_mask_to_base(vcpu, mask);
+ int offset = -1;
+
+ for (;;) {
+ offset = find_next_bit(mask, KVMI_NUM_MSR, offset + 1);
+
+ if (offset >= KVMI_NUM_MSR)
+ break;
+
+ kvm_x86_ops.control_msr_intercept(vcpu, msr_base + offset,
+ MSR_TYPE_W, false);
+ }
+
+ bitmap_zero(mask, KVMI_NUM_MSR);
+}
+
int kvmi_arch_cmd_control_intercept(struct kvm_vcpu *vcpu,
unsigned int event_id, bool enable)
{
@@ -460,9 +530,13 @@ void kvmi_arch_breakpoint_event(struct kvm_vcpu *vcpu, u64 gva, u8 insn_len)
static void kvmi_arch_restore_inter...
2019 Aug 09
0
[RFC PATCH v6 55/92] kvm: introspection: add KVMI_CONTROL_MSR and KVMI_EVENT_MSR
...__exit void hardware_unsetup(void)
free_kvm_area();
}
+static void vmx_msr_intercept(struct kvm_vcpu *vcpu, unsigned int msr,
+ bool enable)
+{
+ struct vcpu_vmx *vmx = to_vmx(vcpu);
+ unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
+
+ vmx_set_intercept_for_msr(msr_bitmap, msr, MSR_TYPE_W, enable);
+}
+
static void vmx_cr3_write_exiting(struct kvm_vcpu *vcpu,
bool enable)
{
@@ -7844,6 +7853,7 @@ static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
.cpu_has_accelerated_tpr = report_flexpriority,
.has_emulated_msr = vmx_has_emulated_msr,
+ .msr_intercept = vmx_msr_...
2020 Feb 07
78
[RFC PATCH v7 00/78] VM introspection
...rospection: add vCPU related data
Nicu?or C??u (19):
KVM: x86: add kvm_arch_vcpu_set_regs()
KVM: x86: add .bp_intercepted() to struct kvm_x86_ops
KVM: x86: add .cr3_write_intercepted()
KVM: x86: add .desc_intercepted()
KVM: x86: export .msr_write_intercepted()
KVM: x86: use MSR_TYPE_R, MSR_TYPE_W and MSR_TYPE_RW with AMD code too
KVM: svm: pass struct kvm_vcpu to set_msr_interception()
KVM: vmx: pass struct kvm_vcpu to the intercept msr related functions
KVM: x86: add .control_singlestep()
KVM: x86: export kvm_arch_vcpu_set_guest_debug()
KVM: x86: export kvm_inject_pending_excepti...
2020 Jul 21
87
[PATCH v9 00/84] VM introspection
...):
KVM: x86: add kvm_arch_vcpu_set_regs()
KVM: x86: add .bp_intercepted() to struct kvm_x86_ops
KVM: x86: add .cr3_write_intercepted()
KVM: svm: add support for descriptor-table exits
KVM: x86: add .desc_intercepted()
KVM: x86: export .msr_write_intercepted()
KVM: x86: use MSR_TYPE_R, MSR_TYPE_W and MSR_TYPE_RW with AMD
KVM: svm: pass struct kvm_vcpu to set_msr_interception()
KVM: vmx: pass struct kvm_vcpu to the intercept msr related functions
KVM: x86: add .control_singlestep()
KVM: x86: export kvm_arch_vcpu_set_guest_debug()
KVM: x86: export kvm_inject_pending_exception()
KV...
2013 Sep 23
57
[PATCH RFC v13 00/20] Introduce PVH domU support
This patch series is a reworking of a series developed by Mukesh
Rathor at Oracle. The entirety of the design and development was done
by him; I have only reworked, reorganized, and simplified things in a
way that I think makes more sense. The vast majority of the credit
for this effort therefore goes to him. This version is labelled v13
because it is based on his most recent series, v11.
2019 Aug 09
117
[RFC PATCH v6 00/92] VM introspection
The KVM introspection subsystem provides a facility for applications running
on the host or in a separate VM, to control the execution of other VM-s
(pause, resume, shutdown), query the state of the vCPUs (GPRs, MSRs etc.),
alter the page access bits in the shadow page tables (only for the hardware
backed ones, eg. Intel's EPT) and receive notifications when events of
interest have taken place
2019 Aug 09
117
[RFC PATCH v6 00/92] VM introspection
The KVM introspection subsystem provides a facility for applications running
on the host or in a separate VM, to control the execution of other VM-s
(pause, resume, shutdown), query the state of the vCPUs (GPRs, MSRs etc.),
alter the page access bits in the shadow page tables (only for the hardware
backed ones, eg. Intel's EPT) and receive notifications when events of
interest have taken place